Hardware

Use CoreInfo to determine processor capabilities

Scott Lowe shows you the CoreInfo utility, which is useful for providing processor information you need, particularly whether or not your processor supports hardware-based virtualization extensions.

In general, when you buy a new server, you have a pretty good idea that the processor supports the features that you need. For example, if you're planning to use the server as a virtualization host, then you'll probably buy a server that supports AMD-V or Intel VT-x extensions. However, when you're repurposing a server, you might not always know exactly what processor is in the system and, although that's easy to find out, you still need to discover the exact capabilities inherent in that system so that you know how it can be purposed.

Fortunately, the good folks in Microsoft's SysInternals unit have the perfect utility for your processor identification arsenal, and it does a whole lot more than just tell you whether or not your processor supports hardware-based virtualization extensions.

However, understanding virtualization capabilities is as good a place as any to start. Once you've downloaded and extracted the coreinfo.exe utility from Microsoft's website, execute coreinfo -v and you'll get results like the ones below.

C:\>coreinfo -v
Coreinfo v3.01 - Dump information on system CPU and memory topology
Copyright (C) 2008-2011 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Xeon(R) CPU           X3440  @ 2.53GHz
Intel64 Family 6 Model 30 Stepping 5, GenuineIntel
HYPERVISOR      -       Hypervisor is present
VMX             *       Supports Intel hardware-assisted virtualization
EPT             *       Supports Intel extended page tables

You'll note that there isn't a lot of information here, but you can see that this processor does, in fact, support Intel hardware-assisted virtualization. Also note that the processor make and model is listed. Finally, notice that this processor also supports Intel's extended page tables/second level address translation (SLAT). If this happened to be an AMD processor, it would show up in a row called NP (nested paging tables).

That's good and all, but CoreInfo does a whole lot more if you omit the -v parameter. You get all kinds of good details about the processors in your system. I'm not going to go over each and every processor feature (but may do so in a future column), but you can see if a particular feature is present by looking for asterisks between the short feature name and the description.

Take a look at the output below.

C:\ >coreinfo
Coreinfo v3.01 - Dump information on system CPU and memory topology
Copyright (C) 2008-2011 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Xeon(R) CPU           X3440  @ 2.53GHz
Intel64 Family 6 Model 30 Stepping 5, GenuineIntel
HTT             -       Hyperthreading enabled
HYPERVISOR      -       Hypervisor is present
VMX             *       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
EM64T           *       Supports 64-bit mode
SMX             *       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
EIST            *       Supports Enhanced Intel Speedstep
NX              *       Supports no-execute page protection
PAGE1GB         -       Supports 1GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4-MB pages
PSE36           *       Supports > 32-bit address 4-MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
FPU             *       Implements i387 FP instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2
AES             -       Supports AES extensions
AVX             -       Supports AVX intruction extensions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTTR            *       Supports Memory Type Range Registers
XSAVE           -       Supports XSAVE/XRSTOR instructions
OSXSAVE         -       Supports XSETBV/XGETBV instructions
CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supprots CMPXCHG16B instruction
DCA             -       Supports prefetch from memory-mapped device
F16C            -       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT isntructions
MOVBE           -       Supports MOVBE instruction
PCLULDQ         -       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
SEP             *       Supports fast system call instructions
DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          *       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
xTPR            *       Supports disabling task priority messages
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC
CNXT-ID         -       L1 data cache mode adaptive or BIOS
MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin
PSN             -       Implements 96-bit processor serial number
Logical to Physical Processor Map:
**------  Physical Processor 0 (Hyperthreaded)
--**----  Physical Processor 1 (Hyperthreaded)
----**--  Physical Processor 2 (Hyperthreaded)
------**  Physical Processor 3 (Hyperthreaded)
Logical Processor to Socket Map:
********  Socket 0
Logical Processor to NUMA Node Map:
********  NUMA Node 0
Logical Processor to Cache Map:
**------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**------  Instruction Cache   0, Level 1,   32 KB, Assoc   4, LineSize  64
**------  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
--**----  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----  Instruction Cache   1, Level 1,   32 KB, Assoc   4, LineSize  64
--**----  Unified Cache       1, Level 2,  256 KB, Assoc   8, LineSize  64
----**--  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--  Instruction Cache   2, Level 1,   32 KB, Assoc   4, LineSize  64
----**--  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
------**  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**  Instruction Cache   3, Level 1,   32 KB, Assoc   4, LineSize  64
------**  Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
********  Unified Cache       4, Level 3,    8 MB, Assoc  16, LineSize  64
Logical Processor to Group Map:
********  Group 0

Getting CoreInfo

You can download CoreInfo from Microsoft's website. The file that you download will have just two files inside the compressed package. The only one that you need to worry about is the file named CoreInfo.exe.

Copy CoreInfo.exe to a directory on your server and, from an elevated command prompt, execute it. You will get output like that shown above.

About

Since 1994, Scott Lowe has been providing technology solutions to a variety of organizations. After spending 10 years in multiple CIO roles, Scott is now an independent consultant, blogger, author, owner of The 1610 Group, and a Senior IT Executive w...

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