Software

Intel's new 3-D transistor is good news for smartphone users

Intel has figured out how to increase performance and battery life at the same time. And Moore's Law keeps on truckin'.

News flash: Intel's new 22nm 3-D Tri-Gate Transistor will perpetuate Moore's Law for years to come.

If Moore's Law isn't doing it for you (I'll try again later), how about this: What if your current smartphone responded like an uber-fast PC, and the battery wasn't drained after a four-hour Skype call?

Interested now?

Apply those improvements to anything that has a chip in it -- from mighty web servers to tiny pacemakers -- and you'll understand what Intel has done. A friend who specializes in hardware engineering likens it to a Formula One race car with the fuel mileage of a Toyota Prius.

I was skeptical. Typically, performance is improved or power consumption reduced, never both at the same time. So, how did Intel pull it off? Not one, but two innovations were shoehorned into the same project.

Intel shrank the fabrication process to use 22 nanometer (nm=billionths of a meter) nodes. Next, Intel departed from traditional planar (2-D) gates, using instead 3-D Tri-Gate technology. Let's look at the reduction in circuit size, first.

To improve performance, semiconductor houses including Intel want to shrink the current 32nm fabrication process. Not that processors using the 32nm fabrication process are slouches. You may recognize the Intel processors in Figure A, all of which use 32nm nodes. Figure A

Image courtesy Intel

If that's true, why work so hard and spend so much money to shrink something only 10 nanometers? Moore's Law is why. I told you I'd get back to it. Gordon Moore, Ph.D. and co-founder of Intel made a bold prediction in 1965:

"The number of transistors incorporated in a chip will approximately double every 24 months."

Time has proven Dr. Moore a visionary:

"For more than four decades, Intel has delivered the challenge of Moore's Law. However, a fundamental barrier is emerging --technology is approaching atomic dimensions. Intel is already working on technologies to overcome this."

The clock is ticking. The current 32nm fabrication process is more than two years old.

In order to double the number of transistors, scientists need the fabrication process to use 22nm nodes, which means circuit paths not much thicker than single atoms. This must-see video by Mark Bohr, Intel fellow and lead on the new 22nm manufacturing process, provides perspective.

Well, they pulled it off. Intel got the 22nm fabrication process to work, getting the right number of transistors to fit in a useable form factor. Moore's Law is safe for another two years, when the fabrication process will use 14nm nodes. Tick, tock.

Impressive as that is, it's time to discuss a new technology that is equally profound. Conventional transistors are planar devices, using a 2-D conducting channel as depicted in Figure B. Figure B

Image courtesy Intel

The same slide illustrates Intel's new approach where three surfaces form conducting channels, hence the term 3-D Tri-Gate. The photographs below provide a rather unique context, allowing us to see something only nanometers wide.

Figure C

32nm planar gates (Image courtesy Intel Press Kit)
Figure D

22nm 3-D Tri-Gates (Image courtesy Intel Press Kit)

So that's how they did it. Now, let's look at what it all means.

Intel has all sorts of graphs and statistics about the 22nm 3-D Tri-Gate transistors, perfect for my engineer friend, but not me. Knowing that, he summarized the new transistor:

  • 40% increase in performance at low voltage when compared to 32nm 2-D transistors.
  • Consumes half the power at the same performance level as 32nm 2-D transistors.

Intel expects to have the first microprocessor using 22nm 3-D Tri-Gate transistors (code-named Ivy Bridge) in production by late 2012. One can only imagine what the digital future will hold when technology surrounding something ubiquitous as a transistor leapfrogs.

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22 comments
realvarezm
realvarezm

It is so exciting see this improvements, but this people have a long way ahead. It will posible in ten years to have a strategy game with virtual reality inside my head just plug trough a helmet or someting like that! Cant wait

kschlotthauer
kschlotthauer

I am excited about the future of what Intel is doing. In the end we can argue 2D vs 3D, but, I am more interested in faster graphics on my PC, less battery drain on my smartphone. I am not the scientist guy, I am the real user guy that likes to have the fastest and latest and with Intel going from 32nm to 22nm and then eventually 14nm...it is a win win for all consumers. I think eventually they will do some sort of "Doc Brown" mumbo jumbo and when they get to the sub-atomic level they will invent some sort of "Atom linking" to speed things up. I remember back in the 80's Bill Gates was quoted as saying "No one will ever need more than 640k of memmory"......uh, yeah right!. I always ask my teenage kids (19,18,15), "I wonder what you guys will be into (technology wise) when you are my age (47)?". With Intel and Moore's law.....I think Holgraphic video conferncing......"Help me Obi-Wan, your our last hope"

AnsuGisalas
AnsuGisalas

That alone is huge! Adding a whole other dimension, from 2D to 3D, that is nothing short of a mind-breaker! Not so much that it wasn't to be expected, it's a pretty obvious trail to follow, but when you look at what it means to the machine, with all the cascades of interactions that follow from that... that's what boggles the mind. Then, how far can it be refined? It might take years to squeeze the maximum effect out of this, with all the little permutations and neat tricks to be invented... Ow. My head hurts.

Slayer_
Slayer_

Finally a chance for those 10ghz processors we have been promised for years. I can just imagine the next video card, 5000 processors running at 2 GHZ each. Using the same power as an old nv8800.

Realvdude
Realvdude

Kind of captures the cheesy yet informatiive disneysque, like the animation demonstration in Jurasic Park. From a technical perspective, tri-gate seems a contour intuitive name for something used in logic, since the design has no impact on the logical function.

Michael Kassner
Michael Kassner

Intel's 3-D transistor dramatically improves performance while lowering power requirements. Envision fast smartphones with batteries lasting twice as long.

Michael Kassner
Michael Kassner

You might miss something. I just read where researchers are using light to trigger parts of the brain. Stay tuned.

Michael Kassner
Michael Kassner

I struggle trying to understand the details of what chip developers are accomplishing. The video really drives it home. A bit older than you (a lot really), yet, I wonder the same thing. What's around the next corner.

santeewelding
santeewelding

You can see they also inscribed the entire Gutenberg Bible along one edge as placation to heathen electrons.

Michael Kassner
Michael Kassner

Intel needed this badly as ARM was making serious in-roads

Lightning Joe
Lightning Joe

Truly complex natural-format brushes in our paint programs, that can update in real time... (...swoon...)

Michael Kassner
Michael Kassner

I had not thought of that aspect. It took me a bit to get used to 3-D somewhat referring to three surfaces.

AnsuGisalas
AnsuGisalas

If I understand you correctly, it's already slated for two years down... It's important to remember here, that there's only so much left : it's not like the number can reach 0

AnsuGisalas
AnsuGisalas

and the words "We come in peace!". The next thing I notice is, that this 2D is really 1D - each object is a line, and a line is a one-dimensional. The new and improved "nano-waffle" is a two-dimensional object (In all these assertions I take the "minimum height", 32nm and 22nm respectively, out of the equation... what remains is the relevant dimensionality). With a one-dimensional basic segment, you have two "ends" to it. With two-dimensional waffling, you have four ends. (+100%) Getting to a truly three-dimensional grid/matrix would require slapping an "above" and a "below" onto the waffle. Doing that would give rise to six ends, a diminished return (only 50%), but still a good gain, if viable. Of course, once you go to above and below, you have an additional parameter for improvement: How many waffles can you stack?

Michael Kassner
Michael Kassner

That is what makes Dr. Moore's prediction so amazing.

AnsuGisalas
AnsuGisalas

"Optimal" is always relative to a set of desired parameters. I want "Optimally Safe", but I figure a race car driver wants "Optimally safe that doesn't detract from Optimal handling during acceleration". I've been thinking about the "Never ease off during a skid" remark, and I just can't see it. That's what I should always do. Now, if I have the drive wheel in the front, and the front wheels have better traction - then I would have to pour on the power to regain control. It's a choice that locks down my options, and forces the speed increase. So, I'm just wondering if we have different ideas of "Optimal", could that explain the difference?

Michael Kassner
Michael Kassner

Your definition seemingly tied them together. Is that always the case?

AnsuGisalas
AnsuGisalas

I once heard about a method for assigning non-integer dimensions to different objects. For example a curved line isn't one-dimensional, but it's not fully two-dimensional, either (in that train of thought), so it would be for example 1,2-dimensional. That can get tricky if we consider, that a line can curve in more than two dimensions, so that it would take a three-dimensional space to contain it. By the way, it occurred to me, that while race-car drivers usually are to be trusted on safe driving, they might have professional reasons not to prefer the optimally safe solution when it comes to the [b]drive wheel[/b] - if the optimal solution means having less traction for acceleration. Just a thought.

Michael Kassner
Michael Kassner

And, it is what the industry is promoting, but it does not compute correctly to general knowledge of 3-dimensional space.

AnsuGisalas
AnsuGisalas

After all, it's just what has to be there. In saying that the 32 nm array is two-dimensional it's already established that the default dimensionality is not counted: After all the 32 nm array is really three-dimensional, since it's 32 nm tall, 32 nm wide, and then quite a bit lot longer, too. The relevant "shape" of the "2D" transistor set is one-dimensional (a line), but it's realized as a three-dimensional construction (32 nm tall and 32 nm wide). Likewise, the relevant "shape" of the "3D" transistor set is two-dimensional (a waffle), but it's realized as a three-dimensional construction (a 22 nm wide and 22 nm tall lattice). I know I'm probably not being very clear about this - but I you start from the fact that the 2D transistor set is a practical impossibility, then pursue it from there, you'll get there.

Michael Kassner
Michael Kassner

If you are referring to real-world conditions, how can you have anything that is only one-dimensional or even two-dimensional? Most consider the 32 nm and 22 nm refer to to the expected average half-pitch of a memory cell at this technology level. While researching this article, I found that the process number is somewhat nebulous.

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