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European Design and Automation Association
(16 results)-
White Papers
Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage
March 18, 2009, 12:00am PDT
Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware,...
Provided by European Design and Automation Association
-
White Papers
Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories
January 12, 2011, 12:00am PST
Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties,...
Provided by European Design and Automation Association
-
White Papers
pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems
February 18, 2010, 12:00am PST
Parallel programming techniques have become one of the great challenges in the transition from single-core to multicore architectures. In this paper, the authors investigate the parallelization of...
Provided by European Design and Automation Association
-
White Papers
Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers
April 19, 2011, 12:00am PDT
The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation...
Provided by European Design and Automation Association
-
White Papers
Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC - A Case Study
February 18, 2010, 12:00am PST
In this paper, the authors examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. They present several design choices and focus on the...
Provided by European Design and Automation Association
-
Whitepapers
Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers
December 13, 2012, 12:00am PST
Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe...
Provided by European Design and Automation Association
-
White Papers
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
February 11, 2008, 12:00am PST
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limited energy storage....
Provided by European Design and Automation Association
-
White Papers
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications
February 10, 2008, 12:00am PST
The next generation of wireless systems will require low-power multi-standard chipsets that are capable to operate over a number of different communication protocols, signal conditions, battery...
Provided by European Design and Automation Association
-
White Papers
DRAM Selection and Configuration for Real-Time Mobile Systems
December 10, 2011, 12:00am PST
The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map....
Provided by European Design and Automation Association
-
White Papers
Memory-Map Selection for Firm Real-Time SDRAM Controllers
December 9, 2011, 12:00am PST
A modern real-time embedded system must support multiple concurrently running applications. To reduce costs, critical SoC components like SDRAM memories are often shared between applications with...
Provided by European Design and Automation Association
-
White Papers
A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
December 10, 2011, 12:00am PST
Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC...
Provided by European Design and Automation Association
-
White Papers
Architectures and Modeling of Predictable Memory Controllers for Improved System Integration
December 15, 2010, 12:00am PST
Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with real-time requirements execute in parallel. System resources, such as memories, are shared...
Provided by European Design and Automation Association
-
White Papers
An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems
December 15, 2010, 12:00am PST
FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug...
Provided by European Design and Automation Association
-
White Papers
Optimal Scheduling of Switched FlexRay Networks
December 15, 2010, 12:00am PST
This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent...
Provided by European Design and Automation Association
-
White Papers
Recursion-Driven Parallel Code Generation for Multi-Core Platforms
March 14, 2009, 12:00am PDT
The authors present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursive...
Provided by European Design and Automation Association
-
White Papers
Compositional System-Level Design Exploration With Planning of High-Level Synthesis
March 16, 2012, 12:00am PDT
The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the...
Provided by European Design and Automation Association
-
Whitepapers
Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers
December 13, 2012, 12:00am PST
Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe...
Provided by European Design and Automation Association
-
White Papers
Compositional System-Level Design Exploration With Planning of High-Level Synthesis
March 16, 2012, 12:00am PDT
The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the...
Provided by European Design and Automation Association
-
White Papers
Recursion-Driven Parallel Code Generation for Multi-Core Platforms
March 14, 2009, 12:00am PDT
The authors present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursive...
Provided by European Design and Automation Association
-
White Papers
Optimal Scheduling of Switched FlexRay Networks
December 15, 2010, 12:00am PST
This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent...
Provided by European Design and Automation Association
-
White Papers
An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems
December 15, 2010, 12:00am PST
FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug...
Provided by European Design and Automation Association
-
White Papers
Architectures and Modeling of Predictable Memory Controllers for Improved System Integration
December 15, 2010, 12:00am PST
Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with real-time requirements execute in parallel. System resources, such as memories, are shared...
Provided by European Design and Automation Association
-
White Papers
A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
December 10, 2011, 12:00am PST
Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC...
Provided by European Design and Automation Association
-
White Papers
Memory-Map Selection for Firm Real-Time SDRAM Controllers
December 9, 2011, 12:00am PST
A modern real-time embedded system must support multiple concurrently running applications. To reduce costs, critical SoC components like SDRAM memories are often shared between applications with...
Provided by European Design and Automation Association
-
White Papers
DRAM Selection and Configuration for Real-Time Mobile Systems
December 10, 2011, 12:00am PST
The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map....
Provided by European Design and Automation Association
-
White Papers
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications
February 10, 2008, 12:00am PST
The next generation of wireless systems will require low-power multi-standard chipsets that are capable to operate over a number of different communication protocols, signal conditions, battery...
Provided by European Design and Automation Association
-
White Papers
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
February 11, 2008, 12:00am PST
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limited energy storage....
Provided by European Design and Automation Association
-
White Papers
Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC - A Case Study
February 18, 2010, 12:00am PST
In this paper, the authors examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. They present several design choices and focus on the...
Provided by European Design and Automation Association
-
White Papers
Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers
April 19, 2011, 12:00am PDT
The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation...
Provided by European Design and Automation Association
-
White Papers
pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems
February 18, 2010, 12:00am PST
Parallel programming techniques have become one of the great challenges in the transition from single-core to multicore architectures. In this paper, the authors investigate the parallelization of...
Provided by European Design and Automation Association
-
White Papers
Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories
January 12, 2011, 12:00am PST
Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties,...
Provided by European Design and Automation Association
-
White Papers
Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage
March 18, 2009, 12:00am PDT
Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware,...
Provided by European Design and Automation Association
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