AICIT

Displaying 1-40 of 332 results

  • White Papers // Mar 2014

    An Efficient Real-Time Multiprocessor Scheduling Algorithm

    Most currently existing optimal real-time multiprocessor scheduling algorithms follow the fairness rule, in which all tasks are forced to make progress in their executions proportional to their utilization, to ensure the optimality of the algorithm. However, obeying the fairness rule results in large number of task preemptions and migrations and...

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  • White Papers // Jan 2014

    Energy- Aware Scheduling of Scientific Workflows Using Discrete PSO in Grids

    Many of the emerging scientific applications are in need of enormous computing power, large data bases, visualization tools, data sets etc. The workload in the grid environment is increasing prominently. Scheduling this workload to the resources has become endure. Resources often consist of tens or hundreds or thousands of processors....

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  • White Papers // Dec 2013

    Performance Estimation Technique for an On-Chip Bus Employing Fixed Priority Arbitration Policy

    In this paper, the authors present the bus model for predicting an on-chip bus throughput at the beginning of the SoC design cycle. In particular, they focus on analyzing the effect of the employed bus arbitration policy on the performance of a target SoC design, in particular, a multimedia SoC...

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  • White Papers // Oct 2013

    Enhancing Energy-Aware Scheduling for Parallel Applications on a Cloud

    As the need for large computing power for executing a parallel application shifted toward cloud computing, an efficient scheduling algorithm is critical the operation of a cloud data center. With the requiring an excellent performance and efficient energy consumption on a cloud, the efficient scheduling is important issue to accomplish...

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  • White Papers // Sep 2013

    Average-Case Performance of a Segmented Asynchronous SRAM Design

    The authors present an asynchronous SRAM system dividing multiple regions to improve the performance in this paper. As growing the number of memory regions, the hardware complexity is increase and the performance is enhanced. Thus, there is a trade-off between the performance and the hardware complexity. They analyze the relationship...

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  • White Papers // Jul 2013

    Design of Reference Model for Complex Embedded Software Testing

    As information telecommunication industry develops and systems get integrated gradually, the importance of complex embedded software testing is growing significantly. On the contrary, the reliability of complex embedded software testing has worsened. Accordingly, testing of software is an essential part in designing and building up embedded system and the volume...

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  • White Papers // Jul 2013

    Digital Single-Side Band Modulation Using Digital Signal Processor

    In this paper, the authors describe the design of a digital single-side band amplitude modulator with 40 kHz output using high-performance digital signal processor for ultrasonic transmitters. The baseband signal is converted to zero-IF signal by using quadrature frequency converter. Then zero-IF signal is filtered by two low-pass filter and...

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  • White Papers // Jun 2013

    Implementation of Physical Layer Communication Protocol for Cloud Storage System Based on FPGA

    The serial communication has the advantages of faster transformation speed, less interference and interface complexity, et, al, so it is widely used in cloud storage system. Cloud storage applies the network technology to manage the storage devices to work together and it will be the development trend of storage technology....

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  • White Papers // May 2013

    Power Consumption of the Shared L2 Cache Dynamic Partition in CMP

    With the trend towards Chip Multi-Processors (CMP), the size of Cache increases apparently. But these caches propose larger and larger proportion in the total power consumption. This paper proposes a new mechanism that implemented in CMP to reduce energy consumption, which based on dynamically way-adaptable cache. The mechanism mainly consists...

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  • White Papers // May 2013

    Priority-Hash Scheduling Algorithm for Embedded Operating Systems

    The scheduling algorithm is one of the most important portions of embedded operating systems. The performance of scheduling algorithm will influence the performance of the whole system. This paper puts forward a new scheduling algorithm that is called priority-hash scheduling algorithm. The important parts of the scheduling algorithm, priority bitmap...

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  • White Papers // May 2013

    Calculation Method of Multi-Core Dynamic Reconfigurable Cache Power Consumption

    With the fast development of semiconductor technology, multi-core processors have gradually replaced single-core processors. The demand of cache is also increasing. Cache, as the most important component of the architecture, occupies the most of the chip's area. It is also the main source of power consumption. If one were to...

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  • White Papers // May 2013

    Low Power Dissipation Model Analysis for Embedded Systems

    Embedded systems serve diverse functionalities to meet the requirement for Computer, Communication equipment, Consumer electronics and Car (4C) products. It results the need of embedded systems to exponential growth. While hundreds of thousand embedded systems run on every corner of daily life, the consumed power consumption is extremely huge. As...

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  • White Papers // May 2013

    Using Grey Decision to FPGA Multi-Tasking Scheduling Reconfigurable Systems

    Recently, the FPGA hardware tasks scheduling have become the focal study. Most of the existing papers researched on single objective optimal operation of reconfigurable assembly line. Although it can get the optimal result, it can spend the high cost in other aspects. Therefore, the single-objective is not an optimal scheme....

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  • White Papers // May 2013

    Conditional Fault Diagnosability of Pancake Graphs

    Distributed processor architectures offer the potential advantage of high speed, provided that they are highly fault tolerant and reliable, and have good communication between remote processors. An important component of such a distributed system is its graph topology, which defines the inter-processor communication architecture. The growing size of a multiprocessor...

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  • White Papers // May 2013

    A Genetic-Based Task Scheduling Algorithms on Heterogeneous Computing Systems to Minimize Makespan

    In this paper, A Genetic-based Task Scheduling (GATS) algorithm on heterogeneous computing systems is developed in order to obtain the minimal makespan that the algorithm combines the techniques of Genetic algorithm and Heterogeneous Earliest Finish Time (HEFT). In a distributed environment, an application is usually decomposed into several independent and/or...

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  • White Papers // Apr 2013

    Design and Evaluation of Shared Buffer for Triplet-Based Hierarchical Interconnection Network

    Buffers play an important role in the design of router architecture, which makes the efficient flow control. Traditional buffer design for Triplet-Based Hierarchical Interconnection Network (TBHIN) adopts the standard design, that is, each virtual channel owns a fixed number of buffers, which leads to insufficient availability of this critical resource....

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  • White Papers // Apr 2013

    Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

    With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a Network-on-Chip (NoC) dynamic and...

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  • White Papers // Apr 2013

    Realization of Real-Time DVD Burning Device of DVD for Embedded Streaming Media

    In this paper, the authors apply real-time DVD recording technology in security system. According to the characteristics of real-time DVD recording technology, the paper expounds respectively on DVD file system structure, UDF file system and real-time recording principle. DVD real-time recording software and hardware is realized in embedded system, it...

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  • White Papers // Apr 2013

    A Composition Algorithm of Enhanced Embedded Web Security Service

    In this paper, the authors discuss the web security composition problem in distributed embedded computing environment. Due to the limited resources of terminal devices in distributed embedded network, the devices usually collaborate in order to accomplish a specific task. To the information disclosure issues caused by not considering the protection...

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  • White Papers // Apr 2013

    The Performance Analysis Based on Heterogeneous Parallel Processors for Anisotropic Diffusion Filters

    A noise in digital image degrades the performance of image processing. These images are most often used in medical field for diagnosis and treatment. Thus, there is a huge demand for high quality images from the medical field. The current algorithms to process useable images are derived using Gaussian blur...

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  • White Papers // Apr 2013

    TM-Based Optimization in Parallel Computing

    To optimize the performance of parallel programming in the multi-core environment, Signature-based conflict detection used in Software Transactional Memory (STM) is introduced. And NAS Parallel Benchmark (NPB) is chosen as the benchmark in the experiments. By analyzing the IS test program, some modifications are done to improve its performance. And...

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  • White Papers // Mar 2013

    Design a Dynamically Shared Buffer with Prefetching for Multiple Virtual Channel Network on Chip

    Due to limited area and power budget in NoC design, DAMQ buffer is usually used to decrease buffer requirements, especially in NoC with multiple virtual channels. DAMQ-PF, a novel dynamically shared buffer schematic is proposed. In DAMQ-PF, multiple virtual channels dynamically share the same data buffer, and a small prefetching...

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  • White Papers // Mar 2013

    A Novel Embedded Software Reliability Model and Its Application

    In this paper, the authors suggest novel reliability models for the embedded software systems. The main ideas of their approach are to consider effects of hardware related software failures on the software reliability model and to incorporate them with the random based model and Weibull based model. All unknown parameters...

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  • White Papers // Mar 2013

    Programmable Scheduling Based on Multi-Core Processor

    Traditional multi-processor interconnection structure cannot be suitable for highly integrated SoC multi-core processor because of high resource overhead, and NoC can solve the problem of multi-core processor interconnection on SoC with high-bandwidth, low power, scalability and parallel communication. Based on multi-core NoC simulation platform, task-oriented NoC scheduling policy is proposed,...

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  • White Papers // Mar 2013

    Design of Fiscal Processor Based on Improved Simple NandFlash File System

    A fiscal processor system which adopts uC/OS-II as the embedded operating system was designed based on Ecog CPU. An improved NandFlash file system was proposed to overcome the storage-consuming and time-consuming problems of general NandFlash file systems. Furthermore, in the proposed fiscal processor, the FAT16 file system was also transplanted...

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  • White Papers // Mar 2013

    A Distributed Evolutionary Algorithm for Multiprocessors Selection

    With the rapid development of the multiprocessor architecture, it is urgent to propose algorithms which can support lots of tasks in parallel on a multiprocessor system, and solve the problems of load balance of processors and stable high-throughput of the system. This paper presents an evolutionary game model for dynamic...

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  • White Papers // Feb 2013

    Research on Reliable Network-on-Chip Architecture Using Asynchronous Logic

    The development of silicon technology follows Moore's law and integrated circuits enter deep submicron era. New technology makes System-On-Chip (SoC) design more difficult: on one hand, logic and wire delays become unpredictable; on the other hand, SoC integrate a large number Intelligence Properties. The exponential development of Integrated Circuits (IC)...

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  • White Papers // Feb 2013

    Application-Specific NoC Topology Synthesis Using Improved Genetic Algorithm

    In future nanoscale era, thousands of Intellectual Property (IP) cores would be able to be integrated onto a little chip forming a powerful System-on-Chip (SoC). Typically, most SoCs, which instinctively are heterogeneous and application-specific, require efficient interconnection topologies. However, traditional on-chip interconnections are bus-based inter-connection structure, and cannot fit the...

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  • White Papers // Feb 2013

    QoS-Prediction Cloud Service Recommendation by Collaborative Filtering in Cloud Manufacturing Platform

    By analyzing the user and cloud service characteristics in cloud manufacturing, combined with the existing classic collaborative filter recommendation method, a recommendation algorithm for user oriented cloud service based QoS prediction in cloud manufacturing was proposed. To meet the needs of user-oriented personalized recommendation service on cloud manufacturing platform, the...

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  • White Papers // Feb 2013

    Register File Load Balanced VLIW Scheduling for Distributed Register Files

    Distributed register files is better than traditional centralized register file in area, delay and power dissipation, and is widely used in clustered VLIW processors. However, the load imbalance among the register files makes the register file cannot be effectively used. High peak register demand of the register files often lead...

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  • White Papers // Feb 2013

    Applications of a TransFLash in an Embedded System Debugging

    In this paper, the hardware and software design for using a TF card in debugging an embedded system are described. The used hardware platform is designed based on a PXA310 application processor. The Android open source operating system is used as the software platform. The design of the connection circuit...

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  • White Papers // Feb 2013

    An Efficient Low Power Test for NoC(Network-on-Chip)

    In this paper, the authors propose the low power test framework for Network-on-Chip (NoC), which is based on embedded processor and on-chip network. The possibility of using embedded processor and on-chip network is introduced and evaluated with benchmark system to test the other embedded cores. A new generation method of...

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  • White Papers // Feb 2013

    One Vehicle Type Recognition System Based On DM6467

    Based on a dual-core chip of digital signal processor DM6467, this paper presents a method on a system of automatic vehicle type recognition from the video and describes the system's hardware architecture. In the algorithm of vehicle type recognition, the authors can distinguish the key-frames from the video for the...

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  • White Papers // Feb 2013

    Optimizing FDTD Computations Using GPGPU with CPML

    The advancements of General Purpose Graphic Processing Units (GPGPUs) have paved the way for computationally intensive scientific calculations to be done on an off-the-shelf massively parallel graphic processors GPUs, rather than the use of expensive solutions such as High Performance Clusters (HPCs) or supercomputers. In this paper, the NVIDIA's Compute...

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  • White Papers // Jan 2013

    Multi-Level Cache Prediction and Partitioning Mechanism in CMP

    In the Chip Multi-Processor (CMP) environment, the LRU replacement algorithm of high associativity multi-level cache has seriously hindered the improvement of the whole system performance. One major reason is that in the LRU replacement algorithm, a cache block, after its last use, remains in the cache for a long time...

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  • White Papers // Jan 2013

    Energy Consumption Modeling Algorithm for Structural Level Oriented Embedded Software

    In this paper, the authors examine a new measure of energy consumption modeling algorithm in structural level based on fuzzy mathematics and BP neural network, which overcomes the difficulties found in other specific nonlinear functional measures: poor fitting action, low computing rate and efficiency. Based on the model as the...

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  • White Papers // Jan 2013

    A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number

    Genetic Algorithm (GA) is one of optimization algorithm based on an idea for evolution of life. GA can be applied various combination optimization problem. This paper proposes a parallel processor for Distributed Genetic Algorithm (DGA) with redundant binary number. Since a redundant binary number has redundancy, solution expression becomes variegated....

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  • White Papers // Jan 2013

    Research on the Application of Bacteria Foraging Optimization Algorithm in Multi-Task Scheduling of Embedded System

    To improve efficiency and load balance in the multi-core processor task scheduling, this paper proposes an improved multi-core processor task scheduling method for the improved bacteria forage optimization algorithm. Randomly generate direct acyclic graph for the multi-core processor task, construct a mathematical model under multi-constraint condition and solve the model...

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  • White Papers // Jan 2013

    Performance Optimization of Massively Parallel FDTD Computations

    The advancements of General Purpose Graphic Processing Units (GPGPUs) have paved the way for computationally intensive scientific calculations to be done on an off the shelf massively parallel graphic processors GPUs, rather than the use of expensive solutions such as high performance clusters HPCs or supercomputers. In this paper, the...

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  • White Papers // Jan 2013

    Cache Replacement Policies for Embedded Mobile Systems: Performance and Power Consumption

    With fast advances in processor technology, imbalance between the relative speeds of processors and the main memory is the rapidly enlarged. To mitigate it, an increasingly larger portion of the chip transistors budget is dedicated for on-chip cache usage, leading to an ever expanding memory hierarchy. As the key for...

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