Association for Computing Machinery

Displaying 1-40 of 6660 results

  • White Papers // Jan 2015

    Compiler Management of Communication and Parallelism for Quantum Computation

    Quantum Computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast...

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  • White Papers // Jan 2015

    A Symbolic Execution Algorithm for Constraint-Based Testing of Database Programs

    In so-called constraint-based testing, symbolic execution is a common technique used as a part of the process to generate test data for imperative programs. Databases are ubiquitous in software and testing of programs manipulating databases is thus essential to enhance the reliability of software. In this paper, the authors propose...

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  • White Papers // Jan 2015

    CQIC: Revisiting Cross-Layer Congestion Control for Cellular Networks

    With the advent of high-speed cellular access and the overwhelming popularity of Smartphone's, a large percent of today's Internet content is being delivered via cellular links. Due to the nature of long-range wireless signal propagation, the capacity of the last hop cellular link can vary by orders of magnitude within...

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  • White Papers // Jan 2015

    Utility of the OpenAccess Database in Academic Research

    Twenty years ago, there was a common design tool which was free and open-source and satisfied the needs of many academic circuit designers. The proliferation of OpenAccess is opening promising new research opportunities to academic communities. The benefits of adopting an OpenAccess based approach to EDA research are growing, and...

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  • White Papers // Dec 2014

    GRAPHITE: An Extensible Graph Traversal Framework for Relational Database Management Systems

    Graph traversals are a basic but fundamental ingredient for a variety of graph algorithms and graph-oriented queries. To achieve the best possible query performance, they need to be implemented at the core of a database management system that aims at storing, manipulating, and querying graph data. Increasingly, modern business applications...

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  • White Papers // Dec 2014

    Uncovering Network Tarpits with Degreaser

    Network tarpits, whereby a single host or appliance can masquerade as many fake hosts on a network and slow network scanners, are a form of defensive cyber-deception. In this paper, the authors develop degreaser, an efficient fingerprinting tool to remotely detect tarpits. In addition to validating their tool in a...

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  • White Papers // Nov 2014

    Design-Theoretic Encoding of Deterministic Hypotheses as Constraints and Correlations Into U-Relational Databases

    In view of the paradigm shift that makes science ever more data-driven, in this paper the authors consider deterministic scientific hypotheses as uncertain data. In the form of mathematical equations, hypotheses symmetrically relate aspects of the studied phenomena. For computing predictions, however, deterministic hypotheses are used asymmetrically as functions. They...

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  • White Papers // Nov 2014

    Patterns in the Chaos - A Study of Performance Variation and Predictability in Public IaaS Clouds

    Benchmarking the performance of public cloud providers is a common research topic. Previous paper has already extensively evaluated the performance of different cloud platforms for different use cases, and under different constraints and experiment setups. In this paper, the authors present a principled, large-scale literature review to collect and codify...

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  • White Papers // Nov 2014

    Analysis of SSL Certificate Reissues and Revocations in the Wake of Heartbleed

    Central to the secure operation of a Public Key Infrastructure (PKI) is the ability to revoke certificates. While much of users' security rests on this process taking place quickly, in practice, revocation typically requires a human to decide to reissue a new certificate and revoke the old one. Thus, having...

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  • White Papers // Nov 2014

    PixelVault: Using GPUs for Securing Cryptographic Operations

    Protecting the confidentiality of cryptographic keys in the event of partial or full system compromise is crucial for containing the impact of attacks. The Heartbleed vulnerability of April 2014, which allowed the remote leakage of secret keys from HTTPS web servers, is an indicative example. In this paper, the authors...

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  • White Papers // Nov 2014

    Faces in the Distorting Mirror: Revisiting Photo-based Social Authentication

    In an effort to hinder attackers from compromising user accounts, Facebook launched a form of two-factor authentication called Social Authentication (SA), where users are required to identify photos of their friends to complete a log-in attempt. Recent research, however, demonstrated that attackers can bypass the mechanism by employing face recognition...

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  • White Papers // Nov 2014

    Handcrafted Fraud and Extortion: Manual Account Hijacking in the Wild

    Online accounts are inherently valuable resources - both for the data they contain and the reputation they accrue over time. Unsurprisingly, this value drives criminals to steal, or hijack, such accounts. In this paper, the authors focus on manual account hijacking - account hijacking performed manually by humans instead of...

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  • White Papers // Nov 2014

    Search + Seizure: The Effectiveness of Interventions on SEO Campaigns

    Black hat Search Engine Optimization (SEO), the practice of abusively manipulating search results, is an enticing method to acquire targeted user traffic. In turn, a range of interventions - from modifying search results to seizing domains - are used to combat this activity. In this paper, the authors examine the...

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  • White Papers // Nov 2014

    Challenges in Inferring Internet Interdomain Congestion

    The authors introduce and demonstrate the utility of a method to localize and quantify inter-domain congestion in the Inter-net. Their Time Sequence Latency Probes (TSLP) method depends on two facts: internet traffic patterns are typically diurnal, and queues increase packet delay through a router during periods of adjacent link congestion....

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  • White Papers // Nov 2014

    Characterizing Large-Scale Click Fraud in ZeroAccess

    Click fraud is a scam that hits a criminal sweet spot by both tapping into the vast wealth of online advertising and exploiting that ecosystem's complex structure to obfuscate the flow of money to its perpetrators. In this paper, the authors illuminate the intricate nature of this activity through the...

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  • White Papers // Nov 2014

    On The Security of Mobile Cockpit Information Systems

    Recent trends in aviation have led many general aviation pilots to adopt the use of iPads (or other tablets) in the cockpit. While initially used to display static charts and documents, uses have expanded to include live data such as weather and traffic information that is used to make flight...

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  • White Papers // Nov 2014

    Computing Multi-Relational Sufficient Statistics for Large Databases

    Databases contain information about which relationships do and do not hold among entities. To make this information accessible for statistical analysis requires computing sufficient statistics that combine information from different database tables. Such statistics may involve any number of positive and negative relationships. With a naive enumeration approach, computing sufficient...

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  • White Papers // Nov 2014

    Multiplierless Design of Folded DSP Blocks

    In this paper, the authors address the problem of minimizing the implementation cost of the Time-Multiplexed Constant Multiplication (TMCM) operation that realizes the multiplication of an input variable by a single constant selected from a set of multiple constants at a time. It presents an efficient algorithm, called ORPHEUS that...

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  • White Papers // Oct 2014

    SoftMoW: Recursive and Reconfigurable Cellular WAN Architecture

    The current LTE network architecture is organized into very large regions, each having a core network and a radio access network. The core network contains an Internet edge comprised of Packet data network GateWays (PGWs). The radio network consists of only base stations. There are minimal interactions among regions other...

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  • White Papers // Oct 2014

    PRAN: Programmable Radio Access Networks

    With the continued exponential growth of mobile traffic and the rise of diverse applications, the current LTE Radio Access Network (RAN) architecture of cellular operators faces mounting challenges. Current RAN suffers from insufficient radio resource coordination, inefficient infrastructure utilization, and inflexible data paths. The authors present the high level design...

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  • White Papers // Oct 2014

    Sweet Little Lies: Fake Topologies for Flexible Routing

    Link-state routing protocols (e.g., OSPF and IS-IS) are widely used because they are scalable, robust, and based on simple abstractions. Unfortunately, these protocols are also relatively inflexible, since they direct all traffic over shortest paths. In contrast, Software Defined Networking (SDN) offers fine-grained control over routing, at the expense of...

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  • White Papers // Oct 2014

    Tango: Simplifying SDN Control with Automatic Switch Property Inference, Abstraction, and Optimization

    A major benefit of Software-Defined Networking (SDN) over traditional networking is simpler and easier control of network devices. The diversity of SDN switch implementation properties, which include both diverse switch hardware capabilities and diverse control-plane software behaviors, however, can make it difficult to understand and/or to control the switches in...

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  • White Papers // Oct 2014

    Blender: Upgrading Tenant-based Data Center Networking

    In this paper, the authors present Blender, a framework that enables network operators to improve tenant performance by tailoring the network's behavior to tenant needs. Tenants may upgrade their provisioned portion of the network with specific features, such as multi-path routing, isolation, and failure recovery, without modifying hosted application code....

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  • White Papers // Oct 2014

    System-Level Memory Optimization for High-Level Synthesis of Component-Based SoCs

    The design of specialized accelerators is essential to the success of many modern systems-on-chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which...

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  • White Papers // Oct 2014

    Automatic Custom Instruction Identification in Memory Streaming Algorithms

    Application-Specific Instruction Set Processors (ASIPs) extend the instruction set of a general purpose processor by dedicated Custom Instructions (CIs). In the last decade, reconfigurable processors advanced this concept towards runtime reconfiguration to increase the efficiency and adaptivity. Compiler support for automatic identification and implementation of ASIP CIs exists commercially and...

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  • White Papers // Oct 2014

    Measurement and Analysis of OSN Ad Auctions

    Advertising is ubiquitous on the web; numerous ad networks serve billions of ads daily via keyword or search term auctions. Recently, Online Social Networks (OSNs) such as Facebook have created site-specific ad services that differ from traditional ad networks by letting advertisers bid on users rather than keywords. With Facebook's...

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  • White Papers // Oct 2014

    Beyond CPM and CPC: Determining the Value of Users on OSNs

    Not all of the over one billion users of Online Social Networks (OSNs) are equally valuable to the OSNs. The current business model of monetizing advertisements targeted to users does not appear to be based on any visible grouping of the users. The primary metrics remain CPM (Cost Per Mille...

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  • White Papers // Oct 2014

    Stream-Oriented Network Traffic Capture and Analysis for High-Speed Networks

    Intrusion detection, traffic classification, and other network monitoring applications need to analyze the captured traffic beyond the network layer to allow for connection-oriented analysis, and achieve resilience to evasion attempts based on TCP segmentation. Existing network traffic capture frameworks, however, provide applications with raw packets and leave complex operations like...

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  • White Papers // Sep 2014

    Security and QoS Tradeoff Recommendation System (SQT-RS) for Dynamic Assessing CPRM-based Systems

    Context-based Parametric Relationship Models (CPRM) defines complex dependencies between different types of parameters. In particular, security and QoS relationships that may occur at different levels of abstraction are easily identified using CPRM. However, the growing number of parameters and relationships, typically due to the heterogeneous scenarios of future networks, increase...

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  • White Papers // Sep 2014

    Poster - iSync: A High Performance and Scalable Data Synchronization Protocol for Named Data Networking

    In this paper, the authors present a high performance synchronization protocol for Named Data Networking (NDN). The protocol, called iSync, uses a two-level Invertible Bloom Filter (IBF) structure to support efficient data reconciliation. Multiple differences can be found by subtracting a remote IBF from a local IBF, and therefore, from...

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  • White Papers // Sep 2014

    Consumer-Producer API for Named Data Networking

    As a new architecture, NDN requires a new API. Today's socket API cannot be reused for NDN communication because its foundational concept is point-to-point virtual channel that does not exist in NDN. This paper presents a new network programming interface to NDN communication protocols and architectural modules. This new API...

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  • White Papers // Sep 2014

    On the Role of Routing in Named Data Networking

    A unique feature of Named Data Networking (NDN) is that its forwarding plane can detect and recover from network faults on its own, enabling each NDN router to handle network failures locally without relying on global routing convergence. This new feature prompts the authors to re-examine the role of routing...

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  • White Papers // Sep 2014

    VIP: A Framework for Joint Dynamic Forwarding and Caching in Named Data Networks

    Emerging information-centric networking architectures seek to optimally utilize both bandwidth and storage for efficient content distribution. This highlights the need for joint design of traffic engineering and caching strategies, in order to optimize network performance in view of both current traffic loads and future traffic demands. The authors present a...

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  • White Papers // Sep 2014

    Kite: A Mobility Support Scheme for NDN

    Named Data Networking (NDN) natively supports the mobility of data consumers through its data-centric design and stateful forwarding plane. However, the mobility support for data producers remains open in the original proposal. In this paper, the authors introduce Kite, a design of mobility support for NDN. Kite leverages the state...

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  • White Papers // Sep 2014

    Automatic Verification of Interactions in Asynchronous Systems with Unbounded Buffers

    Asynchronous communication requires message queues to store the messages that are yet to be consumed. Verification of interactions in asynchronously communicating systems is challenging since the sizes of these queues can grow arbitrarily large during execution. In fact, behavioral models for asynchronously communicating systems typically have in finite state spaces,...

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  • White Papers // Sep 2014

    A Bi-Objective Cost Model for Database Queries in a Multi-Cloud Environment

    Cost models are broadly used in query processing to drive the query optimization process, accurately predict the query execution time, schedule database query tasks, apply admission control and derive resource requirements to name a few applications. The main role of cost models is to produce the time needed to run...

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  • White Papers // Sep 2014

    Proximity-Based Wireless Access Control through Considerate Jamming

    As diverse types of wireless devices emerge, it becomes difficult to apply the existing wireless security measures to them without efforts. Those devices lack conventional user interfaces or they are resource-constrained to process the security protocols. Meanwhile, many of them are used within a geographical boundary to access to the...

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  • White Papers // Sep 2014

    Rethink Energy Accounting with Cooperative Game Theory

    Energy accounting determines how much a software principal contributes to the total system energy consumption. It is the foundation for evaluating software and for operating system based energy management. While various energy accounting policies have been tried, there is no known way to evaluate them directly simply because it is...

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  • White Papers // Sep 2014

    Combating Inter-cell Interference in 802.11ac-based Multi-user MIMO Networks

    In an 802.11ac-based MU-MIMO network comprised of multiple cells, inter-cell interference allows only a single AP to serve its clients at the same time, significantly limiting the network capacity. In this paper, the authors overcome this limitation by letting the APs and clients in interfering cells coordinately cancel the inter-cell...

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  • White Papers // Sep 2014

    Enfold: Downclocking OFDM in WiFi

    Dynamic Voltage and Frequency Scaling (DVFS) has long been used as a technique to save power in a variety of computing domains but typically not in communications devices. A fundamental limit that prevents decreasing the clock frequency is the Nyquist (-Shannon) sampling theorem, which states that the sampling rate must...

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  • White Papers // May 2011

    Scalable Memory Registration for High Performance Networks Using Helper Thread

    Remote DMA (RDMA) enables high performance networks to reduce data copying between an application and the Operating System (OS). However RDMA operations in some high performance networks require communication memory explicitly registered with the network adapter and pinned by the OS. Memory registration and pinning limits the flexibility of the...

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  • White Papers // Dec 2013

    Linearly Compressed Pages: A Low-Complexity, Low-Latency Main Memory Compression Framework

    Data compression is a promising approach for meeting the increasing memory capacity demands expected in future systems. Unfortunately, existing compression algorithms do not translate well when directly applied to main memory because they require the memory controller to perform non-trivial computation to locate a cache line within a compressed memory...

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  • White Papers // Jun 2011

    Six Degrees of Scientific Data: Reading Patterns for Extreme Scale Science IO

    Petascale science simulations generate 10s of TBs of application data per day, much of it devoted to their check-point/restart fault tolerance mechanisms. Previous paper demonstrated the importance of carefully managing such output to prevent application slowdown due to IO blocking, resource contention negatively impacting simulation performance and to fully exploit...

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  • White Papers // Jun 2011

    Memory Power Management via Dynamic Voltage/Frequency Scaling

    Energy efficiency and energy-proportional computing have become a central focus in enterprise server architecture. As thermal and electrical constraints limit system power, and datacenter operators become more conscious of energy costs, energy efficiency becomes important across the whole system. There are many proposals to scale energy at the data-center and...

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  • White Papers // Dec 2010

    Storage-Based Intrusion Detection

    Storage-based intrusion detection consists of storage systems watching for and identifying data access patterns characteristic of system intrusions. Storage systems can spot several common intruder actions, such as adding backdoors, inserting Trojan horses, and tampering with audit logs. For example, examination of 18 real intrusion tools reveals that most can...

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  • White Papers // Aug 2013

    Cache Conscious Star-Join in MapReduce Environments

    With the popularity of big data and cloud computing, data parallel framework MapReduce based data warehouse systems are used widely. Column store is a default data placement in these systems. Traditionally star join is a core operation in the data warehouse. However, little related work study star join in column...

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  • White Papers // Aug 2013

    Toward Intersection Filter-Based Optimization for Joins in MapReduce

    MapReduce has become an attractive and dominant model for processing large-scale datasets. However, this model is not designed to directly support operations with multiple inputs as joins. Many studies on join algorithms including Bloom join in MapReduce have been conducted but they still have too much non-joining data generated and...

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  • White Papers // Aug 2013

    i2MapReduce: Incremental Iterative MapReduce

    Iterative computations are widely used in cloud intelligence applications, such as the well-known PageRank algorithm in web search engines, gradient descent algorithm for optimization, and many other iterative algorithms for applications including recommender systems and link prediction. Cloud intelligence applications often perform iterative computations (e.g., PageRank) on constantly changing data...

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  • White Papers // Jun 2010

    Bed-Tree: An All-Purpose Index Structure for String Similarity Search Based on Edit Distance

    Strings are ubiquitous in computer systems and hence string processing has attracted extensive research effort from computer scientists in diverse areas. One of the most important problems in string processing is to efficiently evaluate the similarity between two strings based on a specified similarity measure. String similarity search is a...

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  • White Papers // May 2013

    An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms

    DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering...

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  • White Papers // Jun 2013

    I/O Acceleration with Pattern Detection

    The I/O bottleneck in high-performance computing is becoming worse as application data continues to grow. In this paper, the authors explore how patterns of I/O within these applications can significantly affect the effectiveness of the underlying storage systems and how these same patterns can be utilized to improve many aspects...

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  • White Papers // Mar 2009

    Type-Based Categorization of Relational Attributes

    In this paper, the authors concentrate on categorization of relational attributes based on their data type. Assuming that attribute type/characteristics are unknown or unidentifiable, they analyze and compare a variety of type-based signatures for classifying the attributes based on the semantic type of the data contained therein (e.g., router identifiers,...

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  • White Papers // Jun 2011

    Turbocharging DBMS Buffer Pool Using SSDs

    Flash Solid-State Drives (SSDs) are changing the I/O landscape, which has largely been dominated by traditional Hard Disk Drives (HDDs) for the last 50 years. In this paper, the authors propose and systematically explore designs for using an SSD to improve the performance of a DBMS buffer manager. They propose...

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  • White Papers // Aug 2008

    QueryScope: Visualizing Queries for Repeatable Database Tuning

    Reading and perceiving complex SQL queries has been a time consuming task in traditional database applications for decades. When it comes to decision support systems with automatically generated and sometimes highly nested SQL queries, human understanding or tuning of these workloads becomes even more challenging. This paper explores visualization methods...

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  • White Papers // Jun 2008

    OLTP Through the Looking Glass, and What We Found There

    On-Line Transaction Processing (OLTP) databases include a suite of features - disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading - that were optimized for computer technology of the late 1970's. Advances in modern processors, memories, and networks mean that today's computers are vastly different from those of...

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  • White Papers // Sep 2006

    Performance Tradeoffs in Read-Optimized Databases

    Database systems have traditionally optimized performance for write-intensive workloads. Recently, there has been renewed interest in architectures that optimize read performance by using column-oriented data representation and light-weight compression. This previous work has shown that under certain broad classes of workloads, column-based systems can outperform row-based systems. Previous work, however,...

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  • White Papers // Sep 2006

    Improving Instruction Cache Performance in OLTP

    Instruction-cache misses account for up to 40% of execution time in On-Line Transaction Processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do not allow increases in the size or associativity of instruction caches that would help reduce...

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  • White Papers // Oct 2012

    Using Vector Interfaces to Deliver Millions of IOPS from a Networked Key-value Storage Server

    The performance of Non-Volatile Memories (NVM) has grown by a factor of 100 during the last several years: flash devices today are capable of over 1 million I/Os per second. Unfortunately, this incredible growth has put strain on software storage systems looking to extract their full potential. To address this...

    Provided By Association for Computing Machinery

  • White Papers // Sep 2012

    The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing

    Off-chip main memory has long been a bottleneck for system performance. With increasing memory pressure due to multiple on-chip cores, effective cache utilization is important. In a system with limited cache space, the authors would ideally like to prevent cache pollution, i.e., blocks with low reuse evicting blocks with high...

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  • White Papers // Aug 2012

    RainMon: An Integrated Approach to Mining Bursty Timeseries Monitoring Data

    Metrics like disk activity and network traffic are widespread sources of diagnosis and monitoring information in datacenters and networks. However, as the scale of these systems increases, examining the raw data yields diminishing insight. The authors present RainMon, a novel end-to-end approach for mining time-series monitoring data designed to handle...

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  • White Papers // Aug 2012

    On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-Core Interconnects

    In this paper, the authors present Network-on-Chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case study, they examine network congestion in bufferless NoCs. They show that congestion manifests itself differently in a NoC than in traditional networks. Network...

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  • White Papers // Feb 2014

    CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications

    Parallel programs consist of series of code sections with different Thread-Level Parallelism (TLP). As a result, it is rather common that a thread in a parallel program, such as a GPU kernel in CUDA programs, still contains both sequential code and parallel loops. In order to leverage such parallel loops,...

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  • White Papers // Jun 2013

    Analyzing Locality of Memory References in GPU Architectures

    In this paper, the authors advocate formal locality analysis on memory references of GPGPU kernels. They investigate the locality of reference at different cache levels in the memory hierarchy. At the L1 cache level, they look into the locality behavior at the warp-, the thread block- and the streaming multiprocessor-level....

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  • White Papers // Jun 2013

    Exploiting Uniform Vector Instructions for GPGPU Performance, Energy Efficiency, and Opportunistic Reliability Enhancement

    State-of-art Graphics Processing Units (GPUs) employ the Single-Instruction Multiple-Data (SIMD) style execution to achieve both high computational throughput and energy efficiency. As previous works have shown, there exists significant computational redundancy in SIMD execution, where different execution lanes operate on the same operand values. Such value locality is referred to...

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  • White Papers // Sep 2012

    Shared Memory Multiplexing: A Novel Way to Improve GPGPU Throughput

    On-chip shared memory (a.k.a. local data share) is a critical resource to many GPGPU applications. In current GPUs, the shared memory is allocated when a thread block (also called a workgroup) is dispatched to a Streaming Multiprocessor (SM) and is released when the thread block is completed. As a result,...

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  • White Papers // Jun 2010

    A GPGPU Compiler for Memory Optimization and Parallelism Management

    This paper presents a novel optimizing compiler for general purpose computation on Graphics Processing Units (GPGPU). It addresses two major challenges of developing high performance GPGPU programs: effective utilization of GPU memory hierarchy and judicious management of parallelism. The input to the authors' compiler is a na

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  • White Papers // Mar 2009

    Understanding Software Approaches for GPGPU Reliability

    Even though Graphics Processing Units (GPUs) are becoming increasingly popular for general purpose computing, current (and likely near future) generations of GPUs do not provide hardware support for detecting soft/hard errors in computation logic or memory storage cells since graphics applications are inherently fault tolerant. As a result, if an...

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  • White Papers // Oct 2008

    Deconstructing New Cache Designs for Thwarting Software Cache-based Side Channel Attacks

    Software cache-based side channel attacks present a serious threat to computer systems. Previously proposed counter-measures were either too costly for practical use or only effective against particular attacks. Thus, a recent work identified cache interferences in general as the root cause and proposed two new cache designs, namely Partition-Locked cache...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2013

    RASTER: Runtime Adaptive Spatial/Temporal Error Resiliency for Embedded Processors

    Applying error recovery monotonously can either compromise the real-time constraint, or worsen the power/energy envelope. Neither of these violations can be realistically accepted in embedded system design, which expects ultra efficient realization of a given application. In this paper, the authors propose a HW/SW methodology that exploits both application specific...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2007

    RISPP: Rotating Instruction Set Processing Platform

    Embedded processors are key for rapidly growing application fields ranging from automotive to personal mobile communication/ computation/entertainment etc. In the early 1990s, the term ASIP has emerged denoting processors with an application specific instruction set. They present a far better efficiency in terms of performance/area; MIPS/mW compared to main stream...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2011

    Low-Power Adaptive Pipelined MPSoCs for Multimedia: An H.264 Video Encoder Case Study

    Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time using worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, the authors propose a...

    Provided By Association for Computing Machinery

  • White Papers // Oct 2009

    MinDeg: A Performance-Guided Replacement Policy for Run-Time Reconfigurable Accelerators

    Reconfigurable processors utilize a reconfigurable fabric and may perform runtime reconfigurations to exchange the set of deployed accelerators during application execution. Depending on the application requirements, the high utilization of the reconfigurable fabric leads to a performance improvement compared to non-reconfigurable Application Specific Instructions-set Processor (ASIPs). However, as the reconfiguration...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2012

    Instruction Scheduling for Reliability-Aware Compilation

    Soft errors have emerged as a non-negligible design challenge in hardware/software systems and their importance is likely to increase further in upcoming technology generations because the transistor dimensions and operating/threshold voltages keep on shrinking eventually leading to further reduction of the critical charge. An instruction scheduling technique is presented that...

    Provided By Association for Computing Machinery

  • White Papers // Oct 2011

    Adaptive Resource Management for Simultaneous Multitasking in Mixed-Grained Reconfigurable Multi-Core Processors

    The authors propose a novel scheme for run-time management of mixed-grained reconfigurable fabric for the purpose of simultaneous multi-tasking in multi-core reconfigurable processors. Traditionally, reconfigurable fabrics are allocated to distinct tasks in order to improve the overall performance without considering quality of service of the entire application. They employ a...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2013

    Reliable On-Chip Systems in the Nano-Era: Lessons Learnt and Future Trends

    Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizing reliability have emerged particularly within the last five to ten years. This paper introduces the most prominent reliability concerns from today's points of...

    Provided By Association for Computing Machinery

  • White Papers // Oct 2011

    Reliable Software for Unreliable Hardware: Embedded Code Generation Aiming at Reliability

    Shrinking feature sizes as a result of technology scaling have led to an increased hardware susceptibility to soft errors. Soft errors may cause spurious bit flips in the underlying hardware that may then propagate through the software layer and finally jeopardize software correctness. Extensive reliability-increasing research has been conducted at...

    Provided By Association for Computing Machinery

  • White Papers // Oct 2008

    Symbolic Voter Placement for Dependability-Aware System Synthesis

    In this paper, the authors present a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms into an implementation. This paper is a dependability-aware system synthesis approach that automatically performs a redundant task binding and placement...

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  • White Papers // Jun 2010

    Towards Scalable System-Level Reliability Analysis

    State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: the BDDs exhaust available memory during their construction and/or the final size of the BDDs is, sometimes up to several orders of magnitude, larger than the available...

    Provided By Association for Computing Machinery

  • White Papers // Oct 2011

    Mapping of Applications to MPSoCs

    Miniaturization of electronic components has led to the introduction of complex electronic systems which are integrated onto a single chip, so-called System-on-Chips (SoCs). At the same time, performance requirements have been increasing. The resulting performance requirements can no longer be met by single processor systems. The advent of embedded many-core...

    Provided By Association for Computing Machinery

  • White Papers // Jun 2011

    Symbolic System Synthesis in the Presence of Stringent Real-Time Constraints

    Stringent real-time constraints lead to complex search spaces containing only very few or even no valid implementations. Hence, while searching for a valid implementation a substantial amount of time is spent on timing analysis during system synthesis. This paper presents a novel system synthesis approach that efficiently prunes the search...

    Provided By Association for Computing Machinery