Delft University of Technology

Displaying 1-40 of 302 results

  • White Papers // Apr 2014

    Massivizing Online Games Using Cloud Computing: A Vision

    Online gaming systems are already providing services to an increasing player base, but also to enterprise training, disaster-scenario analysis, and education. Although the current approach services overall hundreds of millions, the predominant industry approach is self-hosting, that is, to buy and operate large-scale infrastructure. This paper cannot scale when the...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Interfacing Operating Systems and Polymorphic Computing Platforms based on the MOLEN Programming Paradigm

    The molen programming paradigm was proposed to offer a general function like execution of the computation intensive parts of the programs on the reconfigurable fabric of the polymorphic computing platforms. Within the molen programming paradigm, the molen set and execute primitives are employed to map an arbitrary function on the...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    The Molen Compiler for Reconfigurable Processors

    In this paper, the authors describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool

    The 2D DWT consists of two 1D DWT in both directions: horizontal filtering processes the rows followed by vertical filtering processes the columns. It is well known that a straightforward implementation of the vertical filtering shows quite different performance with various working set sizes. The only reasonable explanation for this...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Hardware Acceleration of Sequence Alignment Algorithms - An Overview

    Sequence alignment is one of the most important activities in bioinformatics. With the ever increasing volume of data in bioinformatics databases, the time for comparing a query sequence with the available databases is always increasing. Many algorithms have been proposed to perform and accelerate sequence alignment activities. This paper introduces...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator

    In this paper, the authors present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Their designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Profiling Bluetooth and Linux on the Xilinx Virtex II Pro

    In this paper, the authors present profiling results of the Bluetooth standard implemented on the Xilinx Virtex II Pro device. The investigation is performed in two stages. First, they solely focus on the Bluetooth standard and its internal functions. Second, they focus on the Bluetooth standard in conjunction with an...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Compiler-driven FPGA-area Allocation for Reconfigurable Computing

    In this paper, the authors propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem of FPGA-area allocation is presented as a 0-1 integer linear programming problem and efficient solvers are incorporated for finding the optimal solutions. Additionally, they...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Investigation of Single-Cell Dynamic Faults in Deep-Submiron Memory Technologies

    In this paper, a systematic approach to analyze dynamic faults has been described. This paper presents single-cell dynamic fault models for deep-submicron semiconductor memories together with their associated tests (test primitives). The test primitives are evaluated industrially, together with the traditional tests; using 65nm technology 131 Kbytes embedded SRAMs. The...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Motion Estimation and Temporal Up-Conversion on the TM3270 Media-Processor

    The authors present a quantative performance evaluation of several components of a video format conversion algorithm (referred to as Natural Motion (NM)). The implementation platform is a new programmable media-processor, the TM3270, combined with dedicated hardware support. The performance of two compute-intense NM components, Motion Estimation (ME) and Temporal Up-conversion...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    FPGA Implementation of Parallel Histogram Computation

    Parallelization of histogram functions is a challenging problem due to memory collisions. The authors propose a hardware technique to avoid memory collisions. It is called Parallel Histogram Computation (PHC). The hardware implementation of the PHC uses a dual-ported memory. This hardware technique needs two phases to perform the histogram function....

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Parallel FPGA Design of CA CFAR Algorithm

    The authors propose a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on...

    Provided By Delft University of Technology

  • White Papers // Dec 2013

    Embedded Reconfigurable Computing: The ERA Approach

    The growing complexity and diversity of embedded systems - combined with continuing demands for higher performance and lower power consumption - places increasing pressure on embedded platforms designers. The target of the ERA project is to offer a holistic, multi-dimensional methodology to address these problems in a unified framework exploiting...

    Provided By Delft University of Technology

  • White Papers // Nov 2013

    Accurate and Efficient Identification of Worst-Case Execution Time for Multicore Processors: A Survey

    Parallel systems were for a long time confined to high-performance computing. However, with the increasing popularity of multicore processors, parallelization has also become important for other computing domains, such as desktops and embedded systems. Mission-critical embedded software, like that used in avionics and automotive industry, also needs to guarantee real...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    Hierarchies in Networks. Emerging Hybrids of Networks and Hierarchies for Producing Internet Security

    Networked governance is the default modus operandi in Internet governance. Even the provisioning of Internet security heavily relies on non-hierarchical, networked forms of organization. Responses to a large-scale botnets show the prevalence of networked governance on the Internet and provide insight into its strengths and limitations. Networked governance can be...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    3D-COSTAR: A Cost Model for 3D Stacked ICs

    Selecting appropriate and efficient test flow for a 3D Stacked IC (3D-SIC) is crucial for overall cost optimization. This paper presents 3D-COSTAR, a tool that considers costs involved in the whole 3D-SIC chain, including design, manufacturing, test, packaging and logistics (e.g. related to shipping wafers between a foundry and a...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    A Low Cost Method to Tolerate Soft Errors in the NoC Router Control Plane

    In this paper, the authors propose a low cost method to tolerate soft errors in the main NoC router functional units, i.e., routing units, Virtual Channel (VC) allocators, and switch allocators. The idea behind their proposal is to utilize the idle routing units at neighboring input ports to do redundant...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    Virtual Execution Platforms for Mixed-Time-Criticality Systems: The CompSOC Architecture and Design Flow

    System-on-Chips (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non real-time). As a result, they are often developed by different teams or companies, with different Models Of Computation (MOC) such as dataflow, Kahn Process Networks (KPN), or Time-Triggered (TT). SOC functionality and (real-time) performance is verified after...

    Provided By Delft University of Technology

  • White Papers // Sep 2013

    Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing

    In this paper, the authors propose a heterogeneous hardware accelerator architecture to support streaming image processing. Each image in a data-set is pre-processed on a host processor and sent to hardware kernels. The host processor and the hardware kernels process a stream of images in parallel. The convey hybrid computing...

    Provided By Delft University of Technology

  • White Papers // Aug 2013

    Impact of Mid-Bond Testing in 3D Stacked ICs

    In contrast to planar ICs, during the manufacturing of Three-Dimensional Stacked ICs (3D-SICs) several tests such as pre-bond, mid-bond, post-bond and final tests can be applied. This in turn results into a huge number of test flows/strategies. Selecting appropriate and efficient test flow (for given design and manufacturing parameters such...

    Provided By Delft University of Technology

  • White Papers // Aug 2013

    Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation

    Variability in the manufacturing process results in variation in the maximum supported frequency of individual cores in a Multi-Processor System-on-Chip (MPSoC). This variation needs to be considered when performing statistical timing analysis in the system-level design. In this paper, the authors present a framework to estimate the probability distribution of...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    The BTWorld Use Case for Big Data Analytics: Description, MapReduce Logical Workflow, and Empirical Evaluation

    The commoditization of big data analytics, that is, the deployment, tuning, and future development of big data processing platforms such as MapReduce, relies on a thorough understanding of relevant use cases and workloads. In this paper, the authors propose BTWorld, a use case for time-based big data analytics that is...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Noise Reduction on Memory-Based PUFs

    The efficiency and cost of silicon PUF-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses under varying operational circumstances. Error-correcting codes can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Heterogeneous Hardware Accelerators Interconnect: An Overview

    In this paper, the authors present an overview of interconnect solutions for hardware accelerator systems. A number of solutions are presented: bus-based, DMA, crossbar, NoC, as well as combinations of these. The paper proposes analytical models to predict the performance of these solutions and implements them in practice. The jpeg...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    A Software-Based Technique Enabling Composable Hierarchical Preemptive Scheduling for Time-Triggered Applications

    Many embedded real-time applications are typically time-triggered and preemptive schedulers are used to execute tasks of such applications. Orthogonally, composable partitioned embedded platforms use preemptive time-division multiplexing mechanism to isolate applications. Existing composable systems that support two-level scheduling are restricted to cooperative intra-application schedulers, and thus cannot execute the time-triggered...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Security Economics in the HTTPS Value Chain

    Even though the authors increasingly rely on HTTPS to secure Internet communications, several landmark incidents in recent years have illustrated that its security is deeply flawed. They present an extensive multi-disciplinary analysis that examines how the systemic vulnerabilities of the HTTPS authentication model could be addressed. They conceptualize the security...

    Provided By Delft University of Technology

  • White Papers // May 2013

    Scheduling Jobs in the Cloud Using On-demand and Reserved Instances

    A growing number of applications are running in the cloud. Academia and industry are both increasingly using cloud resources as infrastructure to serve their users, due to the elastic, flexible, and pay-as-you-go features of Infrastructure-as-a-Service (IaaS) clouds. Cloud brokers need to lease resources from IaaS clouds cheaply, yet execute the...

    Provided By Delft University of Technology

  • White Papers // May 2013

    3D Stacked Wide-Operand Adders: A Case Study

    In this paper, the authors address the design of wide-operand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end they first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss...

    Provided By Delft University of Technology

  • White Papers // May 2013

    VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling

    Coarse-grained dynamic frequency scaling has been extensively utilized in embedded (multiprocessor) platforms to achieve energy reduction and by implication to extend the autonomy and battery lifetime. In this paper the authors propose to make use of fine-grained frequency scaling, i.e., adjust the frequency at instruction level; to increase the instruction...

    Provided By Delft University of Technology

  • White Papers // Apr 2013

    A Direct Measurement Scheme of Amalgamated Aging Effects with Novel On-Chip Sensor

    Aggressive technology scaling has led to a significant reduction of device reliability. As a consequence Integrated Circuits (ICs) reliability became a major issue and Dynamic Reliability Management (DRM) schemes have been proposed to assure ICs' lifetime reliability. Though, up to date, various aging sensors have been proposed, few of them...

    Provided By Delft University of Technology

  • White Papers // Mar 2013

    Autonomic Cloud-Based Operation of Massively Multiplayer Online Games

    Massively Multiplayer Online Games (MMOGs) are a new type of large-scale distributed application characterized by seamless virtual worlds in which millions of world-wide players act and interact in real-time. The authors propose a cloud-based middleware model for autonomic operation of Massively Multiplayer Online Games (MMOGs) which will allow small and...

    Provided By Delft University of Technology

  • White Papers // Mar 2013

    Sesame: A User-Transparent Optimizing Framework for Many-Core Processors

    In recent years, more and more many-core processors are superseding sequential ones. Increasing parallelism, rather than increasing clock rate, has become the primary engine of processor performance growth, and this trend is likely to continue. With the integration of more computational cores and deeper memory hierarchies on modern processors, the...

    Provided By Delft University of Technology

  • White Papers // Feb 2013

    Adapting Particle Filter Algorithms to Many-Core Architectures

    The particle filter is a Bayesian estimation technique based on Monte Carlo simulation. It is ideal for non-linear, non-Gaussian dynamical systems with applications in many areas, such as computer vision, robotics, and econometrics. Practical use has so far been limited, because of steep computational requirements. In this paper, the authors...

    Provided By Delft University of Technology

  • White Papers // Feb 2013

    Towards an Optimized Big Data Processing System

    To perform fast and inexpensive big data analytics, researchers use a processing system represented by a stack of frameworks for data storage, data processing, and data manipulation deployed over a large distributed system. In the context of the data explosion phenomenon, existing performance models for MapReduce are applicable for specific...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Massivizing Multi-Player Online Games on Clouds

    Massively Multiplayer Online Games (MMOGs) are a new type of large-scale distributed application. For example, the social game FarmVille and similar games attract monthly over one hundred million users. Since the early 2000s, MMOGs are traditional HPC users; for example, World of Warcraft (WoW) deploys globally hundreds of thousands of...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Reliability and Variability Analyses in SRAM Decoder

    Modern Static Random Access Memory (SRAM) systems are susceptible to reliability and variability issues. Examples of reliability and variability issues are Bias Temperature Instability (BTI) in the transistors and resistive/open interconnect defects, respectively. This paper analyzes the impacts of BTI and resistive defects independently as well as simultaneously on the...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Configurable Fault-Tolerance for a Configurable VLIW Processor

    In this paper the authors present the design and implementation of configurable fault-tolerance techniques for a configurable VLIW processor. The processor can be configured for 2, 4, or 8 issue-slots with different types of execution Functional Units (FUs), and its Instruction Set Architecture (ISA) is based on the VEX ISA....

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    Exploring Test Opportunities for Memory and Interconnects in 3D ICs

    3D-Stacked IC (3D-SIC) based on Through-Silicon-Vias (TSV) is an emerging technology that provides many benefits such as low power, high bandwidth 3D memories and heterogeneous integration. One of the attractive applications making use of such benefits is the stacking of memory dies on logic. System integrators for such application have...

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems

    Multicore systems are not only hard to program but also hard to test, debug and maintain. This is because the traditional way of accessing shared memory in multithreaded applications is to use lock-based synchronization, which is inherently non-deterministic and can cause a multithreaded application to have many different possible execution...

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    Impact of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder Reliablity

    Partial open defects in modern Static Random Access Memory (SRAM) address decoders are one of the main causes of small delays; these are hard to detect and may result in escapes and reliability problems. In addition, aging failures -such as Bias Temperature Instability (BTI) - may worsen the situation and...

    Provided By Delft University of Technology

  • White Papers // Nov 2008

    Rule-set Database Inspection: Towards Data Utilization in Packet Processing

    A critical task in network processing is packet analysis that includes operations like packet classification, filtering, and inspection. These operations are commonly based on matching headers and/or data within packets to rules inside a rule-set database. Consequently, the matching procedure determines how packets are classified. When matched, the same database...

    Provided By Delft University of Technology

  • White Papers // Oct 2007

    SARC Power Estimation Methodology

    In modern CMOS technologies, power consumption is becoming a significant challenge for the integrated circuits industry. Accurate estimation of power dissipation is very important during micro-architectural design of every computational structure. This paper presents the methodology the author's intent to use in future investigations regarding power consumption of the SARC...

    Provided By Delft University of Technology

  • White Papers // May 2007

    A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies

    In this paper, the authors present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose is to reduce the latency in executing memory copies aligned on word boundaries. The proposed solution exploits the presence of...

    Provided By Delft University of Technology

  • White Papers // Sep 2008

    Automating defects simulation and fault modeling for SRAMs

    The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes of realistic functional fault models with their corresponding test sequences, is a time consuming...

    Provided By Delft University of Technology

  • White Papers // Oct 2008

    Compiler and OpenMP framework to allow dynamic hardware allocation on reconfigurable platforms

    In this paper, the authors present the compiler and OpenMP runtime library extensions needed to allow runtime decisions regarding area allocation on a reconfigurable platform in a multi application context. Using a strong interaction between the operating system and the compiled applications, their framework will allow operating system algorithms to...

    Provided By Delft University of Technology

  • White Papers // Jun 2008

    Bitstream Compression Techniques for Virtex 4 FPGAs

    In this paper, the authors examine the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardware implementation cost. As their purpose is the acceleration of the configuration process, estimating the decoder speed also plays a major role in...

    Provided By Delft University of Technology

  • White Papers // Mar 2008

    Analyzing Scalability of Deblocking Filter of H.264 via TLP exploitation in a new many-core architecture

    Today's multimedia systems demand more and more computational power since the quality of content that they provide is improving. In this paper, the authors present results of parallelization of Deblocking Filter (DF) of H.264 video codec on Decoupled Threaded Architecture (DTA). They parallelized the code trying to exploit all available...

    Provided By Delft University of Technology

  • White Papers // Jun 2008

    A Low-Cost Cache Coherence Verification Method for Snooping Systems

    Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory in modern multiprocessor systems is supported by cache coherence mechanisms. The correctness of cache coherence of the system is crucial for the data integrity. This...

    Provided By Delft University of Technology

  • White Papers // Aug 2008

    CCproc: An Efficient Cryptographic Coprocessor

    In this paper, the authors introduce CCproc, a symmetric-key cryptographic (co)processor with a custom instruction set optimized for cryptographic applications. They study ten popular crypto algorithms, and provide custom solutions for them, while they also offer general support for future encryption algorithms. They design a custom but simple datapath able...

    Provided By Delft University of Technology

  • White Papers // Sep 2008

    Reconfigurable Architectures in Collaborative Grid Computing: An Approach

    The continuing need for faster high-performance computing is expected to continue in the coming years due to the increasing complexity of scientific and biologic computing applications. These applications are currently moving beyond the realm of geographically bounded supercomputers into distributed grids that tie together many millions of various heterogeneous computing...

    Provided By Delft University of Technology

  • White Papers // Oct 2008

    Matched SAMS Scheme: Supporting Multiple Stride Unaligned Vector Accesses with Multiple Memory Modules

    In this paper, the authors analyze the problem of supporting conflict-free access for multiple stride families in parallel memory schemes targeted for high performance vector processing systems. They propose the Matched SAMS Scheme, which is based on the basic SAMS scheme, to support conflict-free vector memory accesses for strides from...

    Provided By Delft University of Technology

  • White Papers // Sep 2008

    A Chip MultiProcessor Accelerator for Video Decoding

    The authors have entered the era of Chip Multi-Processors (CMPs) and at time of writing they are already being deployed in many market segments. In this paper, they propose architectural enhancements to specialize the Cell SPU for video decoding. Through thorough analysis of the H.264 video decoding kernels they identify...

    Provided By Delft University of Technology

  • White Papers // Sep 2010

    A Multiported Register File with Register Renaming for Configurable Softcore VLIW Processors

    In this paper, the authors present the design and implementation of a BRAM-based multi-ported register file with arbitrary number of read and write ports. In order to avoid the conflicts associated with write ports, they present a register renaming technique that is applied between the compiler and the assembler. This...

    Provided By Delft University of Technology

  • White Papers // Jul 2010

    High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories

    Error Correction Codes (ECCs) are common industrial practices for tolerating intermittent and transient faults in semiconductor memories. They have been also proposed for emerging hybrid nanoelectronic memories. However, this solution comes at higher cost in terms of performance penalty and area overhead. This paper proposes a high performance cluster-fault correction...

    Provided By Delft University of Technology

  • White Papers // May 2010

    Extending the Cell SPE with Energy Efficient Branch Prediction

    Energy-efficient dynamic branch predictors are proposed for the cell SPE, which normally depends on compiler-inserted hint instructions to predict branches. All designed schemes use a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme predecodes instructions...

    Provided By Delft University of Technology

  • White Papers // May 2010

    A Case for Hardware Task Management Support for the StarSS Programming Model

    StarSS is a parallel programming model that eases the task of the programmer. The users has to identify the tasks that can potentially be executed in parallel and the inputs and outputs of these tasks, while the runtime system takes care of the difficult issues of determining inter task dependencies,...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder

    The H.264/AVC intra-only frame encoder, for its excellent encoding performance, is well-suited for image/video compression applications such as Digital Still Camera (DSC), Digital Video Camera (DVC), television studio broadcast and surveillance video. The forward integer transform is an integral part of the H.264/AVC video encoder. In this paper, for image...

    Provided By Delft University of Technology

  • White Papers // Apr 2010

    Power Analysis of Parallel CA-CFAR FPGA Design

    The authors provide a power analysis of a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware, originally proposed by the authors. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence....

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    Runtime Multitasking Support on Reconfigurable Accelerators

    Serving several applications at runtime on a reconfigurable machine is a challenging problem in which the reconfigurable fabric has to be shared among competing tasks. Due to the inherent complexity of assigning tasks to the FPGA, a comprehensive runtime system is required to address all the conflicting issues between competing...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Interfacing Operating Systems and Polymorphic Computing Platforms based on the MOLEN Programming Paradigm

    The molen programming paradigm was proposed to offer a general function like execution of the computation intensive parts of the programs on the reconfigurable fabric of the polymorphic computing platforms. Within the molen programming paradigm, the molen set and execute primitives are employed to map an arbitrary function on the...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    A Composable and Integrable Hardware Compiler for Automated Heterogeneous HW/SW co-design Tool-Chains

    Recent years have showed that the complexity of embedded systems and their architectures is growing rapidly. At the same time, there is a continuous decrease in the time to market. This is due to market demand for more functionality and due to more advanced technologies becoming available and being combined...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    An Efficient FPGA Design of Reverse Converter for the Moduli Set {2n+2,2n+1,2n}

    In this paper the authors point out error in earlier literature and then proposes a novel reverse converter for the moduli set {2n + 2,2n + 1,2n}. A previously proposed scheme is simplified in order to obtain a reverse converter that uses mod-n operations. Next, a low complexity implementation that...

    Provided By Delft University of Technology

  • White Papers // Feb 2010

    A Shared Reconfigurable VLIW Multiprocessor System

    Embedded systems have become commonplace nowadays and they are being utilize for many different applications such as image processing, computer vision, networking, wireless communication, etc. Because these applications offer a good amount of functional and data level parallelism, they can achieve better performance when run on multiprocessor systems rather than...

    Provided By Delft University of Technology

  • White Papers // Feb 2010

    Bit Line Coupling Memory Tests for Single-Cell Fails in SRAMs

    Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper...

    Provided By Delft University of Technology

  • White Papers // Jun 2007

    Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-Ii Pro

    Reconfigurable computing entails the utilization of a general purpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete reconfiguration is needed to change the functionality of the FPGA even when the change is minor. Moreover, the complete chip needs to be halted to perform the reconfiguration....

    Provided By Delft University of Technology

  • White Papers // Jul 2007

    Cache Replacement Policies for IP Address Lookups

    In IP routing, the routing table lookup is a very important operation and the speed in which it is performed determines the overall performance of Internet processors. Consequently, caching schemes are implemented in such processors to speed up these operations. A well-known factor affecting the performance of caches is the...

    Provided By Delft University of Technology

  • White Papers // May 2007

    Design Space Exploration of Configuration Manager for Network Processing Applications

    Current FPGAs provide a powerful platform for network processing applications. The main challenge is the exploitation of the reconfiguration to increase the performance of the system. In this paper, a design space exploration framework is presented to design a reconfigurable platform for multi-service network processing applications. An integrated design flow...

    Provided By Delft University of Technology

  • White Papers // Mar 2007

    Profiling, Compilation, and HDL Generation within the hArtes Project

    The hArtes project addresses research and development issues of embedded systems. It investigates hardware/software integration and builds a general-purpose toolchain, which accepts applications written in a multiplicity of high-level algorithm descriptions and it produces semi automatically a \"Best fit\" mapping of such applications into a heterogeneous reconfigurable system. The tool...

    Provided By Delft University of Technology

  • White Papers // Mar 2007

    Configurable Transactional Memory

    Programming efficiency of heterogeneous concurrent systems is limited by the use of lock-based synchronization mechanisms. Transactional memories can greatly improve the programming efficiency of such systems. In field-programmable computing machines, a conventional fixed transactional memory becomes inefficient use of the silicon. The authors propose Configurable Transactional Memory (CTM) as a...

    Provided By Delft University of Technology

  • White Papers // Mar 2007

    RDM+: a New Mac Layer Real-Time Communication Protocol

    The common feature of modern distributed systems are a large number of devices interconnected together to perform the desired operations. Many real-time communication protocols have been studied to guarantee the communication requirements of distributed real-time systems. But, current techniques lack all or most of these requirements specially bounded message delivery...

    Provided By Delft University of Technology

  • White Papers // Apr 2007

    A Survey of Autonomic Computing Systems

    Data and programs in centralized applications are kept at one site and this is conceived as a bottleneck in performance and availability of remote information in desktop computers. The evolution of networks and Internet has introduced highly scalable and available services making operational environments more complex. The increasing complexity, cost...

    Provided By Delft University of Technology

  • White Papers // Mar 2007

    Performance Evaluation of Real-Time Message Delivery in RDM Algorithm

    Complexity of distributed real-time applications such as automotive electronics has increased dramatically over the last couple of years. As a result, developing communication protocols to address real-time requirements of these applications such as reliability, in time delivery of messages, priority support, and fault-tolerance needs more sophisticated techniques. To satisfy these...

    Provided By Delft University of Technology

  • White Papers // Jan 2007

    Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues

    In this paper, the authors present an overview regarding the synthesis of regular expressions targeting FPGAs. It describes current solutions and a number of open issues. Implementation of regular expressions can be very challenging when performance is critical. Software implementations may not be able to satisfy performance requirements and thus...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    The Molen Compiler for Reconfigurable Processors

    In this paper, the authors describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex...

    Provided By Delft University of Technology

  • White Papers // Nov 2008

    Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion

    Sequence alignment is an important activity in the field of bioinformatics that enables the user to compare DNA strands with each other and promises to help the user understand possible genetically transmitted diseases. In this paper, the authors adapted a novel approach for accelerating the Smith-Waterman (S-W) algorithm using Recursive...

    Provided By Delft University of Technology

  • White Papers // Nov 2008

    Evaluation of SRAM Faulty Behavior Under Bit Line Coupling

    The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool

    The 2D DWT consists of two 1D DWT in both directions: horizontal filtering processes the rows followed by vertical filtering processes the columns. It is well known that a straightforward implementation of the vertical filtering shows quite different performance with various working set sizes. The only reasonable explanation for this...

    Provided By Delft University of Technology

  • White Papers // Sep 2007

    A Cache Architecture for Counting Bloom Filters

    Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., utilizing multi-level memory hierarchies, special hardware architectures, and hardware threading. In this paper, the authors introduce a multi-level memory hierarchy and a special hardware cache architecture for counting Bloom...

    Provided By Delft University of Technology

  • White Papers // Oct 2007

    Parallelism Utilization in Embedded Reconfigurable Computing Systems: A Survey of Recent Trends

    Recently, embedded reconfigurable computing has attracted great attention due to its potential to accelerate application execution. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. Researchers in this field have reported substantial performance improvements for...

    Provided By Delft University of Technology

  • White Papers // Oct 2007

    Analysis of Video Filtering on the Cell Processor

    In this paper, an analysis of bi-dimensional video filtering on the cell broadband engine processor is presented. To evaluate the processor, a highly adaptive filtering algorithm was chosen: the deblocking filter of the H.264 video compression standard. The baseline version is a scalar implementation extracted from the FFMPEG H.264 decoder....

    Provided By Delft University of Technology