Delft University of Technology

Displaying 1-40 of 317 results

  • White Papers // Apr 2014

    Massivizing Online Games Using Cloud Computing: A Vision

    Online gaming systems are already providing services to an increasing player base, but also to enterprise training, disaster-scenario analysis, and education. Although the current approach services overall hundreds of millions, the predominant industry approach is self-hosting, that is, to buy and operate large-scale infrastructure. This paper cannot scale when the...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    The Molen Compiler for Reconfigurable Processors

    In this paper, the authors describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator

    In this paper, the authors present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Their designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Hardware Acceleration of Sequence Alignment Algorithms - An Overview

    Sequence alignment is one of the most important activities in bioinformatics. With the ever increasing volume of data in bioinformatics databases, the time for comparing a query sequence with the available databases is always increasing. Many algorithms have been proposed to perform and accelerate sequence alignment activities. This paper introduces...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool

    The 2D DWT consists of two 1D DWT in both directions: horizontal filtering processes the rows followed by vertical filtering processes the columns. It is well known that a straightforward implementation of the vertical filtering shows quite different performance with various working set sizes. The only reasonable explanation for this...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Profiling Bluetooth and Linux on the Xilinx Virtex II Pro

    In this paper, the authors present profiling results of the Bluetooth standard implemented on the Xilinx Virtex II Pro device. The investigation is performed in two stages. First, they solely focus on the Bluetooth standard and its internal functions. Second, they focus on the Bluetooth standard in conjunction with an...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Compiler-driven FPGA-area Allocation for Reconfigurable Computing

    In this paper, the authors propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem of FPGA-area allocation is presented as a 0-1 integer linear programming problem and efficient solvers are incorporated for finding the optimal solutions. Additionally, they...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Motion Estimation and Temporal Up-Conversion on the TM3270 Media-Processor

    The authors present a quantative performance evaluation of several components of a video format conversion algorithm (referred to as Natural Motion (NM)). The implementation platform is a new programmable media-processor, the TM3270, combined with dedicated hardware support. The performance of two compute-intense NM components, Motion Estimation (ME) and Temporal Up-conversion...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Investigation of Single-Cell Dynamic Faults in Deep-Submiron Memory Technologies

    In this paper, a systematic approach to analyze dynamic faults has been described. This paper presents single-cell dynamic fault models for deep-submicron semiconductor memories together with their associated tests (test primitives). The test primitives are evaluated industrially, together with the traditional tests; using 65nm technology 131 Kbytes embedded SRAMs. The...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Interfacing Operating Systems and Polymorphic Computing Platforms based on the MOLEN Programming Paradigm

    The molen programming paradigm was proposed to offer a general function like execution of the computation intensive parts of the programs on the reconfigurable fabric of the polymorphic computing platforms. Within the molen programming paradigm, the molen set and execute primitives are employed to map an arbitrary function on the...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    Parallel FPGA Design of CA CFAR Algorithm

    The authors propose a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on...

    Provided By Delft University of Technology

  • White Papers // Jan 2014

    FPGA Implementation of Parallel Histogram Computation

    Parallelization of histogram functions is a challenging problem due to memory collisions. The authors propose a hardware technique to avoid memory collisions. It is called Parallel Histogram Computation (PHC). The hardware implementation of the PHC uses a dual-ported memory. This hardware technique needs two phases to perform the histogram function....

    Provided By Delft University of Technology

  • White Papers // Dec 2013

    Embedded Reconfigurable Computing: The ERA Approach

    The growing complexity and diversity of embedded systems - combined with continuing demands for higher performance and lower power consumption - places increasing pressure on embedded platforms designers. The target of the ERA project is to offer a holistic, multi-dimensional methodology to address these problems in a unified framework exploiting...

    Provided By Delft University of Technology

  • White Papers // Nov 2013

    Accurate and Efficient Identification of Worst-Case Execution Time for Multicore Processors: A Survey

    Parallel systems were for a long time confined to high-performance computing. However, with the increasing popularity of multicore processors, parallelization has also become important for other computing domains, such as desktops and embedded systems. Mission-critical embedded software, like that used in avionics and automotive industry, also needs to guarantee real...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    Hierarchies in Networks. Emerging Hybrids of Networks and Hierarchies for Producing Internet Security

    Networked governance is the default modus operandi in Internet governance. Even the provisioning of Internet security heavily relies on non-hierarchical, networked forms of organization. Responses to a large-scale botnets show the prevalence of networked governance on the Internet and provide insight into its strengths and limitations. Networked governance can be...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    3D-COSTAR: A Cost Model for 3D Stacked ICs

    Selecting appropriate and efficient test flow for a 3D Stacked IC (3D-SIC) is crucial for overall cost optimization. This paper presents 3D-COSTAR, a tool that considers costs involved in the whole 3D-SIC chain, including design, manufacturing, test, packaging and logistics (e.g. related to shipping wafers between a foundry and a...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    A Low Cost Method to Tolerate Soft Errors in the NoC Router Control Plane

    In this paper, the authors propose a low cost method to tolerate soft errors in the main NoC router functional units, i.e., routing units, Virtual Channel (VC) allocators, and switch allocators. The idea behind their proposal is to utilize the idle routing units at neighboring input ports to do redundant...

    Provided By Delft University of Technology

  • White Papers // Oct 2013

    Virtual Execution Platforms for Mixed-Time-Criticality Systems: The CompSOC Architecture and Design Flow

    System-on-Chips (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non real-time). As a result, they are often developed by different teams or companies, with different Models Of Computation (MOC) such as dataflow, Kahn Process Networks (KPN), or Time-Triggered (TT). SOC functionality and (real-time) performance is verified after...

    Provided By Delft University of Technology

  • White Papers // Sep 2013

    Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing

    In this paper, the authors propose a heterogeneous hardware accelerator architecture to support streaming image processing. Each image in a data-set is pre-processed on a host processor and sent to hardware kernels. The host processor and the hardware kernels process a stream of images in parallel. The convey hybrid computing...

    Provided By Delft University of Technology

  • White Papers // Aug 2013

    Impact of Mid-Bond Testing in 3D Stacked ICs

    In contrast to planar ICs, during the manufacturing of Three-Dimensional Stacked ICs (3D-SICs) several tests such as pre-bond, mid-bond, post-bond and final tests can be applied. This in turn results into a huge number of test flows/strategies. Selecting appropriate and efficient test flow (for given design and manufacturing parameters such...

    Provided By Delft University of Technology

  • White Papers // Aug 2013

    Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation

    Variability in the manufacturing process results in variation in the maximum supported frequency of individual cores in a Multi-Processor System-on-Chip (MPSoC). This variation needs to be considered when performing statistical timing analysis in the system-level design. In this paper, the authors present a framework to estimate the probability distribution of...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    The BTWorld Use Case for Big Data Analytics: Description, MapReduce Logical Workflow, and Empirical Evaluation

    The commoditization of big data analytics, that is, the deployment, tuning, and future development of big data processing platforms such as MapReduce, relies on a thorough understanding of relevant use cases and workloads. In this paper, the authors propose BTWorld, a use case for time-based big data analytics that is...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Noise Reduction on Memory-Based PUFs

    The efficiency and cost of silicon PUF-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses under varying operational circumstances. Error-correcting codes can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Heterogeneous Hardware Accelerators Interconnect: An Overview

    In this paper, the authors present an overview of interconnect solutions for hardware accelerator systems. A number of solutions are presented: bus-based, DMA, crossbar, NoC, as well as combinations of these. The paper proposes analytical models to predict the performance of these solutions and implements them in practice. The jpeg...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    A Software-Based Technique Enabling Composable Hierarchical Preemptive Scheduling for Time-Triggered Applications

    Many embedded real-time applications are typically time-triggered and preemptive schedulers are used to execute tasks of such applications. Orthogonally, composable partitioned embedded platforms use preemptive time-division multiplexing mechanism to isolate applications. Existing composable systems that support two-level scheduling are restricted to cooperative intra-application schedulers, and thus cannot execute the time-triggered...

    Provided By Delft University of Technology

  • White Papers // Jun 2013

    Security Economics in the HTTPS Value Chain

    Even though the authors increasingly rely on HTTPS to secure Internet communications, several landmark incidents in recent years have illustrated that its security is deeply flawed. They present an extensive multi-disciplinary analysis that examines how the systemic vulnerabilities of the HTTPS authentication model could be addressed. They conceptualize the security...

    Provided By Delft University of Technology

  • White Papers // May 2013

    Scheduling Jobs in the Cloud Using On-demand and Reserved Instances

    A growing number of applications are running in the cloud. Academia and industry are both increasingly using cloud resources as infrastructure to serve their users, due to the elastic, flexible, and pay-as-you-go features of Infrastructure-as-a-Service (IaaS) clouds. Cloud brokers need to lease resources from IaaS clouds cheaply, yet execute the...

    Provided By Delft University of Technology

  • White Papers // May 2013

    3D Stacked Wide-Operand Adders: A Case Study

    In this paper, the authors address the design of wide-operand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end they first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss...

    Provided By Delft University of Technology

  • White Papers // May 2013

    VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling

    Coarse-grained dynamic frequency scaling has been extensively utilized in embedded (multiprocessor) platforms to achieve energy reduction and by implication to extend the autonomy and battery lifetime. In this paper the authors propose to make use of fine-grained frequency scaling, i.e., adjust the frequency at instruction level; to increase the instruction...

    Provided By Delft University of Technology

  • White Papers // Apr 2013

    A Direct Measurement Scheme of Amalgamated Aging Effects with Novel On-Chip Sensor

    Aggressive technology scaling has led to a significant reduction of device reliability. As a consequence Integrated Circuits (ICs) reliability became a major issue and Dynamic Reliability Management (DRM) schemes have been proposed to assure ICs' lifetime reliability. Though, up to date, various aging sensors have been proposed, few of them...

    Provided By Delft University of Technology

  • White Papers // Mar 2013

    Autonomic Cloud-Based Operation of Massively Multiplayer Online Games

    Massively Multiplayer Online Games (MMOGs) are a new type of large-scale distributed application characterized by seamless virtual worlds in which millions of world-wide players act and interact in real-time. The authors propose a cloud-based middleware model for autonomic operation of Massively Multiplayer Online Games (MMOGs) which will allow small and...

    Provided By Delft University of Technology

  • White Papers // Mar 2013

    Sesame: A User-Transparent Optimizing Framework for Many-Core Processors

    In recent years, more and more many-core processors are superseding sequential ones. Increasing parallelism, rather than increasing clock rate, has become the primary engine of processor performance growth, and this trend is likely to continue. With the integration of more computational cores and deeper memory hierarchies on modern processors, the...

    Provided By Delft University of Technology

  • White Papers // Feb 2013

    Adapting Particle Filter Algorithms to Many-Core Architectures

    The particle filter is a Bayesian estimation technique based on Monte Carlo simulation. It is ideal for non-linear, non-Gaussian dynamical systems with applications in many areas, such as computer vision, robotics, and econometrics. Practical use has so far been limited, because of steep computational requirements. In this paper, the authors...

    Provided By Delft University of Technology

  • White Papers // Feb 2013

    Towards an Optimized Big Data Processing System

    To perform fast and inexpensive big data analytics, researchers use a processing system represented by a stack of frameworks for data storage, data processing, and data manipulation deployed over a large distributed system. In the context of the data explosion phenomenon, existing performance models for MapReduce are applicable for specific...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Massivizing Multi-Player Online Games on Clouds

    Massively Multiplayer Online Games (MMOGs) are a new type of large-scale distributed application. For example, the social game FarmVille and similar games attract monthly over one hundred million users. Since the early 2000s, MMOGs are traditional HPC users; for example, World of Warcraft (WoW) deploys globally hundreds of thousands of...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Reliability and Variability Analyses in SRAM Decoder

    Modern Static Random Access Memory (SRAM) systems are susceptible to reliability and variability issues. Examples of reliability and variability issues are Bias Temperature Instability (BTI) in the transistors and resistive/open interconnect defects, respectively. This paper analyzes the impacts of BTI and resistive defects independently as well as simultaneously on the...

    Provided By Delft University of Technology

  • White Papers // Jan 2013

    Configurable Fault-Tolerance for a Configurable VLIW Processor

    In this paper the authors present the design and implementation of configurable fault-tolerance techniques for a configurable VLIW processor. The processor can be configured for 2, 4, or 8 issue-slots with different types of execution Functional Units (FUs), and its Instruction Set Architecture (ISA) is based on the VEX ISA....

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    Exploring Test Opportunities for Memory and Interconnects in 3D ICs

    3D-Stacked IC (3D-SIC) based on Through-Silicon-Vias (TSV) is an emerging technology that provides many benefits such as low power, high bandwidth 3D memories and heterogeneous integration. One of the attractive applications making use of such benefits is the stacking of memory dies on logic. System integrators for such application have...

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems

    Multicore systems are not only hard to program but also hard to test, debug and maintain. This is because the traditional way of accessing shared memory in multithreaded applications is to use lock-based synchronization, which is inherently non-deterministic and can cause a multithreaded application to have many different possible execution...

    Provided By Delft University of Technology

  • White Papers // Dec 2012

    Fault Tolerance on Multicore Processors using Deterministic Multithreading

    In this paper the authors describe a software based fault tolerance approach for multithreaded programs running on multicore processors. Redundant multithreaded processes are used to detect soft errors and recover from them. Their scheme makes sure that the execution of the redundant processes is identical even in the presence of...

    Provided By Delft University of Technology

  • White Papers // Oct 2009

    A Novel Non-Iterative Localization Solution

    In this paper, a new method is proposed for low complexity localization based on measured/estimated ranges. First, it is proved that the method provides a better estimator than the well known non-iterative direct methods documented in literature, i.e. the Spherical Interpolation and the Linear Least Squares method. It does so...

    Provided By Delft University of Technology

  • White Papers // Aug 2012

    Benchmarking in the Cloud: What It Should, Can, and Cannot Be

    With the increasing adoption of Cloud Computing, the authors observe an increasing need for Cloud Benchmarks, in order to assess the performance of Cloud infrastructures and software stacks, to assist with provisioning decisions for Cloud users, and to compare Cloud offerings. They understand their paper as one of the first...

    Provided By Delft University of Technology

  • White Papers // Aug 2008

    Investigating peer-to-peer meta-brokering in Grids

    Grid Computing has succeeded in establishing production Grids serving various user communities all around the world. The emerging Web technologies have already affected Grid development; the latest solutions from Peer-To-Peer networking also need to be considered in order to successfully transform the currently separated production Grids to a World-Wide Grid...

    Provided By Delft University of Technology

  • White Papers // Nov 2012

    IaaS Cloud Benchmarking: Approaches, Challenges, and Experience

    Infrastructure-as-a-Service (IaaS) cloud computing is an emerging commercial infrastructure paradigm under which clients (users) can lease resources when and for how long needed, under a cost model that reflects the actual usage of resources by the client. For IaaS clouds to become mainstream technology and for current cost models to...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    How Do Enterprise System Applications Create Business Value for European Firms? New Evidence for the Mediation Effects of Product and Process Innovation

    Despite the ubiquitous proliferation and importance of enterprise system applications, there exists little empirical research on their performance effects, especially among European firms. This paper provides large-sample, economy-wide evidence on the differential effects of enterprise systems adoption on firm performance. It explains how business value is actually created by differentiating...

    Provided By Delft University of Technology

  • White Papers // Sep 2012

    JAG: Reliable and Predictable Wireless Agreement Under External Radio Interference

    Wireless low-power transceivers used in sensor networks typically operate in unlicensed frequency bands that are subject to external radio interference caused by devices transmitting at much higher power. Communication protocols should therefore be designed to be robust against such interference. A critical building block of many protocols at all layers...

    Provided By Delft University of Technology

  • White Papers // Oct 2009

    Analyzing the Effect of Node Mobility in Clustered Wireless Ad Hoc Networks

    Clustering has been used as a fundamental tool to improve scalability in large wireless ad-hoc networks. Techniques based on clustering, such as routing, self-organization, context management, service discovery, etc., ensure QoS in wireless ad-hoc networks when the number of devices increases. The crucial issue of clustering is the overhead generated...

    Provided By Delft University of Technology

  • White Papers // Aug 2010

    Static Consistency Checking of Web Applications With WebDSL

    Modern web application development frameworks provide web application developers with high-level abstractions to improve their productivity. However, their support for static verification of applications is limited. Inconsistencies in an application are often not detected statically, but appear as errors at run-time. The reports about these errors are often obscure and...

    Provided By Delft University of Technology

  • White Papers // Dec 2010

    Interactive Disambiguation of Meta Programs With Concrete Object Syntax

    In meta-programming with concrete object syntax, meta programs can be written using the concrete syntax of manipulated programs. Quotations of concrete syntax fragments and anti-quotations for meta-level expressions and variables are used to manipulate the abstract representation of programs. These small, isolated fragments are often ambiguous and must be explicitly...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    Encapsulating Software Platform Logic by Aspect-Oriented Programming: A Case Study in Using Aspects for Language Portability

    Software platforms such as the Java Virtual Machine or the CLR .NET virtual machine have their own ecosystem of a core programming language or instruction set, libraries, and developer community. Programming languages can target multiple software platforms to increase interoperability or to boost performance. Introducing a new compiler backend for...

    Provided By Delft University of Technology

  • White Papers // Dec 2009

    Natural and Flexible Error Recovery for Generated Parsers

    Parser generators are an indispensable tool for rapid language development. However, they often fall short of the finesse of a hand-crafted parser, built with the language semantics in mind. One area where generated parsers have provided unsatisfactory results is that of error recovery. Good error recovery is both natural, giving...

    Provided By Delft University of Technology

  • White Papers // Jan 2009

    Decorated Attribute Grammars Attribute Evaluation Meets Strategic Programming

    Attribute grammars are a powerful specification formalism for tree-based computation, particularly for software language processing. Various extensions have been proposed to abstract over common patterns in attribute grammar specifications. These include various forms of copy rules to support non-local dependencies, collection attributes, and expressing dependencies that are evaluated to a...

    Provided By Delft University of Technology

  • White Papers // May 2009

    Domain-Specific Languages for Composable Editor Plugins

    Modern IDEs increase developer productivity by incorporating many different kinds of editor services. These can be purely syntactic, such as syntax highlighting, code folding, and an outline for navigation; or they can be based on the language semantics, such as in-line type error reporting and resolving identifier declarations. Building all...

    Provided By Delft University of Technology

  • White Papers // May 2009

    A Pure Object-Oriented Embedding of Attribute Grammars

    Attribute grammars are a powerful specification paradigm for many language processing tasks, particularly semantic analysis of programming languages. Recent attribute grammar systems use dynamic scheduling algorithms to evaluate attributes by need. In this paper, the authors show how to remove the need for a generator, by embedding a dynamic approach...

    Provided By Delft University of Technology

  • White Papers // Oct 2008

    When Frameworks Let You Down: Platform-Imposed Constraints on the Design and Evolution of Domain-Specific Languages

    Application frameworks encapsulate knowledge of a particular domain in a reusable library. However, based on a general-purpose language, these do not provide notational constructs for the particular domain, and are limited to the static checks of the host language. Verification of correctness, security, and style constraints, and optimizations in terms...

    Provided By Delft University of Technology

  • White Papers // Jan 2009

    Experiences With Domain-Specific Language Embedding in Scala

    Embedding Domain-Specific Languages (DSLs) in general-purpose programming languages offers a simpler path to implementation than developing standalone DSL processors. However, sacrifices must be made, particularly in formal analysis of DSL programs. This paper explores these tradeoffs in the context of the Kiama project that is investigating embedding of language processing...

    Provided By Delft University of Technology

  • White Papers // Dec 2011

    Designing Cyber Warfare Information Infrastructure Resilience

    Due to many cyber attacks in the last years, governments are realizing how vulnerable they have become should there be a break out of a cyberwar. This urged them to establish a cyber warfare information infrastructure in a short time. However, this cyber warfare information infrastructure relies heavily on public...

    Provided By Delft University of Technology

  • White Papers // Dec 2008

    Investigating the Global Semantic Impact of Speech Recognition Error on Spoken Content Collections

    Errors in speech recognition transcripts have a negative impact on effectiveness of content-based speech retrieval and present a particular challenge for collections containing conversational spoken content. The authors propose a Global Semantic Distortion (GSD) metric that measures the collection-wide impact of speech recognition error on spoken content retrieval in a...

    Provided By Delft University of Technology

  • White Papers // Dec 2011

    Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield

    As technology scales, the impact of process variation on the MAXimum supported Frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. The...

    Provided By Delft University of Technology

  • White Papers // Jun 2011

    Improved Power Modeling of DDR SDRAMs

    Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power consumption, but lack accurate and generic power models. The most popular SDRAM power model provided by Micron, is found to be inaccurate...

    Provided By Delft University of Technology

  • White Papers // May 2011

    Power Minimisation for Real-Time Dataflow Applications

    Energy efficient execution of applications is important for many reasons, e.g. time between battery charges, device temperature. Voltage and Frequency Scaling (VFS) enables applications to be run at lower frequencies on hardware resources thereby consuming less power. Real-time applications have deadlines that must be met otherwise their output is devalued....

    Provided By Delft University of Technology

  • White Papers // Jun 2011

    PUMA: Placement Unification With Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC

    Platform-based Field Programmable Gate Arrays (FPGAs) have gained popularity for implementing Multi-Processor System on Chips (MPSoCs). The applications in an MPSoC can have high complexities and stringent Quality-of-Service (QoS) demands. Consequently, the problem of binding an application on an FPGA has become more challenging. An application requires logic and communication...

    Provided By Delft University of Technology

  • White Papers // Jun 2011

    A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip

    Modern Field Programmable Gate Arrays (FPGAs) posses small features, and have gained popularity in mission-critical systems. However, due to small FPGA features and harsh external conditions that can be faced by a mission-critical system, an FPGA chip can suffer from faults. This in turn raises the need to test an...

    Provided By Delft University of Technology

  • White Papers // May 2011

    Composable Power Management With Energy and Power Budgets Per Application

    Embedded Multi-Processor Systems-on-Chip (MPSoCs) commonly run multiple applications at once. These applications may have different time criticalities, i.e. non real-time, soft real-time, and firm or hard real-time. Application-level composability is used to provide each application with its own virtual platform, such that each application may be developed, verified, and executed...

    Provided By Delft University of Technology

  • White Papers // Apr 2010

    A Composable, Energy-Managed, Real-Time MPSOC Platform

    Multi-Processors Systems On Chip (MPSOC) platforms emerged in embedded systems as hardware solutions to support the continuously increasing functionality and performance demands in this domain. Such a platform has to execute a mix of applications with diverse performance and timing constraints, i.e., real-time or non-real-time, thus different application schedulers should...

    Provided By Delft University of Technology

  • White Papers // Jun 2010

    On-Chip Network Interfaces Supporting Automatic Burst Write Creation, Posted Writes and Read Prefetch

    Networks-on-Chip are seen as a scalable solution for facilitating the development of Systems-on-Chip with an increasing number of IP cores. Many studies already address the implementation details of such networks and a large effort has been invested in optimizing the routing strategy and the organization of the network, however, by...

    Provided By Delft University of Technology

  • White Papers // Oct 2009

    Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip

    The authors envision that future FPGA will use a Hard-Wired Network on Chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bit-stream for soft IPs). In this paper, they present a reconfiguration methodology which makes use of such a platform to realize composable...

    Provided By Delft University of Technology

  • White Papers // Aug 2009

    Efficient Multicast Support in Buffered Crossbars Using Networks on Chip

    The Internet growth coupled with the variety of its services is creating an increasing need for multicast traffic support by backbone routers and packet switches. Recently, buffered crossbar (CICQ) switches have shown high potential in efficiently handling multicast traffic. However, they were unable to deliver optimal performance despite their expensive...

    Provided By Delft University of Technology

  • White Papers // Jun 2009

    Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration

    Resources in contemporary Systems-on-Chip (SoC) are shared between applications to reduce cost. Access to shared resources is provided by arbiters that require a small hardware implementation and must run at high speed. To manage heavily loaded resources, such as memory channels, it is also important that the arbiter minimizes over...

    Provided By Delft University of Technology

  • White Papers // Jun 2009

    Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors

    Voltage-Frequency Scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tasks of an application. The impact of VFS on the end-to-end application performance is difficult to predict, especially when these tasks are mapped on multiple processors that are...

    Provided By Delft University of Technology

  • White Papers // May 2009

    Composable Resource Sharing Based on Latency-Rate Servers

    Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification complexity increases exponentially with the number of applications and must be repeated if an application is added, removed, or modified. Predictable systems offering lower bounds on performance have been proposed...

    Provided By Delft University of Technology

  • White Papers // Jun 2009

    Internet-Router Buffered Crossbars Based on Networks on Chip

    The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, with line cards that use virtual output-queueing to reduce head-of-line blocking. In this paper, the authors propose to use a multi-hop Network On a Chip...

    Provided By Delft University of Technology

  • White Papers // Mar 2009

    A Network-on-Chip Monitoring Infrastructure for Communication-Centric Debug of Embedded Multi-Processor SoCs

    Problems in a new System On Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of...

    Provided By Delft University of Technology

  • White Papers // Feb 2009

    Modeling Reconfiguration in a FPGA With a Hardwired Network on Chip

    The authors propose that FPGAs use a HardWired Network On Chip (HWNOC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstreams for soft IP). In this paper, they model such a platform. Using the HWNOC applications mapped on hard or soft IPs are set...

    Provided By Delft University of Technology

  • White Papers // Dec 2008

    Aelite: A Flit-Synchronous Network on Chip With Composable and Predictable Services

    To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput bounds. Traditionally, NoC architectures only deliver...

    Provided By Delft University of Technology

  • White Papers // Jan 2012

    A High-Level Debug Environment for Communication-Centric Debug

    A large part of a modern SOC's debug complexity resides in the interaction between the main system components. Transaction-level debug moves the abstraction level of the debug process up from the bit and cycle level to the transactions between IP blocks. In this paper, the authors raise the debug abstraction...

    Provided By Delft University of Technology

  • White Papers // Jan 2012

    Impact of Power-Management Granularity on the Energy-Quality Trade-Off for Soft and Hard Real-Time Applications

    In this paper, the authors introduce the concepts of work of tokens (e.g. video frames) in an application, and slack arising from variations in work. Slack is used for dynamic voltage and frequency scaling in combination with a conservative power-management policy that never misses deadlines, for hard real-time applications, and...

    Provided By Delft University of Technology

  • White Papers // Jan 2012

    Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip

    The authors present a methodology to debug a SOC by concentrating on its communication. Their extended communication model includes: multiple signal groups per interface protocol at each IP port, the handshakes per signal group (e.g. for command), and the handshakes within a signal group (e.g. for write and read data...

    Provided By Delft University of Technology

  • White Papers // Oct 2010

    Handoff in Radio Over Fiber Indoor Networks at 60 GHz

    Wireless indoor networks employing Radio over Fiber technique combining 60GHz wireless networks with wired networks is a new solution to provide high definition in-home multimedia applications. About 5 Gbps is available around 60GHz band. In 60GHz band each antenna can cover a small space such as a single room in...

    Provided By Delft University of Technology

  • White Papers // Mar 2010

    Protection of an Intrusion Detection Engine With Watermarking in Ad Hoc Networks

    In this paper, the authors present an intrusion detection engine comprised of two main elements; firstly, a neural network for the actual detection task and secondly watermarking techniques for protecting the related information that must be exchanged between nodes. In particular, they exploit information visualization and machine learning techniques in...

    Provided By Delft University of Technology