Democritus University of Thrace

Displaying 1-25 of 25 results

  • White Papers // Jan 2015

    Design and Implementation of a Secure Mobile IP Architecture

    The increasing number of portable computers, combined with the requirement for non-stop connections to networks, makes the provision of Internet mobility important. Mobile IP defines protocols and procedures by which a mobile node can exchange packets, regardless of its current point-of-attachment to the Internet, and without changing its IP address....

    Provided By Democritus University of Thrace

  • White Papers // May 2014

    Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms

    Modern multiprocessor heterogeneous systems incorporating multiple hardware accelerators on chip have resulted in an excessive increase in the complexity of hardware/software co-design. Designers have now to explore a design space including both per-accelerator architectural parameters as well as inter-accelerator combinations, i.e. different design configurations among the allocated accelerators, as each...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2014

    A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms

    Field Programmable Gate Arrays (FPGAs) promise a low power flexible alternative for today's market heterogeneous systems. In order to be widely accepted, novel solutions and approaches are required for fast and flexible application implementation. In this paper, the authors propose a methodology, as well as the supporting tool flow targeting...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2014

    On Designing Self-Aware Reconfigurable Platforms

    Existing application domains exhibit variations in terms of complexity, performance and power consumption, whereas their efficient implementation onto general purpose FPGAs (Field Programmable Gate Arrays) is not always a viable solution. In this paper, the authors introduce a framework for designing self-aware reconfigurable platforms. Rather than similar approaches, their solution...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2013

    A Platform-Independent Runtime Methodology for Mapping Multiple Applications Onto FPGAs Through Resource Virtualization

    Field Programmable Gate Arrays (FPGAs) promise a low power flexible alternative for implementing parallel applications. Compared to CPUs (Central Processing Units) and GPUs (Graphics Processing Units), they suffer from slow development cycles due to the high complexity of application development and hardware incompatibilities. Towards this direction, the authors propose a...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2013

    A Framework for Performing Fault-Tolerant Placement Based on Genetic Algorithm

    Fault-tolerance is a crucial challenge for a number of application domains. Existing solutions to this problem are applied uniformly at the entire design imposing among others mentionable delay and power overheads. In this paper, the authors introduce a software-supported framework based on genetic algorithm for supporting fast application placement under...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2012

    An FPGA Implementation of the SURF Algorithm for the ExoMars Programme

    Achieving highly accurate feature extraction in a short period of time is very important for space applications based on computer vision algorithms, such as with the ExoMars programme of ESA (European Space Agency). The paper describes a HW/SW co-design scheme using FPGAs (Field Programmable Gate Arrays) to speed-up the SURF...

    Provided By Democritus University of Thrace

  • White Papers // Nov 2012

    SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    Autonomous rover navigation is a challenging goal for space missions. One of the most critical tasks towards this direction affects the efficient implementation of computer vision algorithms. Apart from their increased computational complexity imposed by these algorithms, additional constraints are posed whenever they are employed for space missions. This paper...

    Provided By Democritus University of Thrace

  • White Papers // Sep 2012

    A Novel Prototyping and Evaluation Framework for NoC-based MPSoC

    In this paper, the authors present a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking test...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2012

    A Privacy-Preserving Cloud Computing System for Creating Participatory Noise Maps

    Participatory sensing is a crowd-sourcing technique which relies both on active contribution of citizens and on their location and mobility patterns. As such, it is particularly vulnerable to privacy concerns, which may seriously hamper the large-scale adoption of participatory sensing applications. In this paper, the authors present a privacy-preserving system...

    Provided By Democritus University of Thrace

  • White Papers // Jun 2012

    Framework for Performing Rapid Evaluation of 3D SoCs

    In recent years, the 3D IC (Integrated Circuit) has attracted increasing attention. Along with technology updates, there are several published works dealing with the 3D physical design problem. Among others, tools for partitioning, floor-plan, placement and routing for 3D architectures have been proposed. These approaches are based almost exclusively on...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2012

    The SPARTAN Project: FPGA-based Implementation of Computer Vision Algorithms Targeting to Space Applications

    The exploration of Mars is one of the main goals for both NASA and ESA, as confirmed by past and recent activities. Vision-based robotics applications have been widely studied in the last years. However, up to now solutions that have been proposed were affecting mostly software level. The SPARTAN project...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2012

    Performance Evaluation of TCP in IEEE 802.16 Networks

    An important application for the IEEE 802.16 technology (also called WiMAX) it to provide high-speed access to the Internet where the Transmission Control Protocol (TCP) is the core transport protocol. In this paper, the authors study through extensive simulation scenarios, the performance characteristics of five representative TCP schemes, namely TCP...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2012

    A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures

    Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2011

    Low-Cost Fault Tolerant Targeting FPGA Devices

    More than at any other time, global economics favor programmable chips over costly ASICs and ASSPs, since the costs and risks associated with application-specific devices can only be justified for a short list of ultra-high volume commodity products. Technology scaling in conjunction to the trend towards higher performance introduces mentionable...

    Provided By Democritus University of Thrace

  • White Papers // Aug 2011

    SPARTAN Project: Efficient Implementation of Computer Vision Algorithms onto Reconfigurable Platform Targeting to Space Applications

    The exploration of Mars is one of the main goals for both NASA and ESA, as confirmed by past and recent activities. Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation...

    Provided By Democritus University of Thrace

  • White Papers // Aug 2011

    A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

    Interconnection structures in FPGAs (Field Programmable Gate Arrays) increasingly contribute more to the delay and power consumption. Three-Dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2010

    A Modified Spiral Search Algorithm and Its Embedded System Architecture Design

    One of the most growing areas in the embedded community is multimedia devices. Multimedia devices incorporate a number of complicated functions for their operation, like motion estimation. A multitude of different implementations have been proposed to reduce motion estimation complexity, such as spiral search. The authors have studied the implementations...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2010

    Comparative Performance Evaluation of Routing Algorithms in IEEE 802.11 Ad Hoc Networks

    In this paper the authors examine the behavior of Ad Hoc networks through simulations, using different routing protocols and various topologies. They examine the difference in performance, using CBR application, with packets of different size through a variety of topologies, showing the impact node placement has on networks performance. They...

    Provided By Democritus University of Thrace

  • White Papers // Feb 2010

    A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs

    In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-Dimensional (3D) architectures are able to...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2010

    Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's

    In this paper, the authors present a design methodology and associated tool chain for efficient design of complex MPSoC architectures implemented using 3D-Stacked Integrated Circuit (3D-SIC). The proposed framework is based on a three step methodology that combines relatively accurate high-level, and two more accurate low-level prototyping tools. The high-level...

    Provided By Democritus University of Thrace

  • White Papers // Nov 2009

    A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations

    In this paper, the authors present a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA (Field Programmable Gate Array) implementation figures are given for various implementation parameters of...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2008

    A Method and Tool for Early Design/technology Search-Space Exploration for 3D ICs

    3D integration is the big next step in system integration. It is still an emerging technology though and its implications on die and packages are not fully understood yet. Furthermore, it comes in many different process flavors. Adoption by mainstream designers requires the availability of tools that let them evaluate...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2008

    A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs

    Using new silicon technologies, increasing logic densities and clock frequencies on FPGAs (Field Programmable Gate Arrays) lead to rapid elevation in power density. Since the power consumption is a critical challenge for designing Three Dimensional (3D) Integrated Circuits (ICs), a novel temperature-aware Placement and Routing (P&R) algorithm targeting to 3D...

    Provided By Democritus University of Thrace

  • White Papers // Oct 2006

    Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

    Power consumption is one of the major headaches, which should be tackled by the designers. Also, the parameters that affect significantly the performance and power are the Configurable Logic Blocks (CLBs) and the interconnection components. A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The main...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2010

    A Modified Spiral Search Algorithm and Its Embedded System Architecture Design

    One of the most growing areas in the embedded community is multimedia devices. Multimedia devices incorporate a number of complicated functions for their operation, like motion estimation. A multitude of different implementations have been proposed to reduce motion estimation complexity, such as spiral search. The authors have studied the implementations...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2010

    Comparative Performance Evaluation of Routing Algorithms in IEEE 802.11 Ad Hoc Networks

    In this paper the authors examine the behavior of Ad Hoc networks through simulations, using different routing protocols and various topologies. They examine the difference in performance, using CBR application, with packets of different size through a variety of topologies, showing the impact node placement has on networks performance. They...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2012

    Performance Evaluation of TCP in IEEE 802.16 Networks

    An important application for the IEEE 802.16 technology (also called WiMAX) it to provide high-speed access to the Internet where the Transmission Control Protocol (TCP) is the core transport protocol. In this paper, the authors study through extensive simulation scenarios, the performance characteristics of five representative TCP schemes, namely TCP...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2012

    A Privacy-Preserving Cloud Computing System for Creating Participatory Noise Maps

    Participatory sensing is a crowd-sourcing technique which relies both on active contribution of citizens and on their location and mobility patterns. As such, it is particularly vulnerable to privacy concerns, which may seriously hamper the large-scale adoption of participatory sensing applications. In this paper, the authors present a privacy-preserving system...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2012

    A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures

    Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected...

    Provided By Democritus University of Thrace

  • White Papers // Feb 2010

    A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs

    In current reconfigurable architectures, the interconnect structures increasingly contribute to the delay and power consumption budget. The demand for increased clock frequencies and logic availability (smaller area foot print) makes the problem even more important, leading among others to rapid elevation in power density. Three-Dimensional (3D) architectures are able to...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2011

    Low-Cost Fault Tolerant Targeting FPGA Devices

    More than at any other time, global economics favor programmable chips over costly ASICs and ASSPs, since the costs and risks associated with application-specific devices can only be justified for a short list of ultra-high volume commodity products. Technology scaling in conjunction to the trend towards higher performance introduces mentionable...

    Provided By Democritus University of Thrace

  • White Papers // Aug 2011

    SPARTAN Project: Efficient Implementation of Computer Vision Algorithms onto Reconfigurable Platform Targeting to Space Applications

    The exploration of Mars is one of the main goals for both NASA and ESA, as confirmed by past and recent activities. Vision-based robotic applications exhibit increased computational complexity. This problem becomes even more important regarding mission critical application domains. The SPARTAN project focuses in the tight and optimal implementation...

    Provided By Democritus University of Thrace

  • White Papers // May 2014

    Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms

    Modern multiprocessor heterogeneous systems incorporating multiple hardware accelerators on chip have resulted in an excessive increase in the complexity of hardware/software co-design. Designers have now to explore a design space including both per-accelerator architectural parameters as well as inter-accelerator combinations, i.e. different design configurations among the allocated accelerators, as each...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2014

    On Designing Self-Aware Reconfigurable Platforms

    Existing application domains exhibit variations in terms of complexity, performance and power consumption, whereas their efficient implementation onto general purpose FPGAs (Field Programmable Gate Arrays) is not always a viable solution. In this paper, the authors introduce a framework for designing self-aware reconfigurable platforms. Rather than similar approaches, their solution...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2014

    A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms

    Field Programmable Gate Arrays (FPGAs) promise a low power flexible alternative for today's market heterogeneous systems. In order to be widely accepted, novel solutions and approaches are required for fast and flexible application implementation. In this paper, the authors propose a methodology, as well as the supporting tool flow targeting...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2008

    A Method and Tool for Early Design/technology Search-Space Exploration for 3D ICs

    3D integration is the big next step in system integration. It is still an emerging technology though and its implications on die and packages are not fully understood yet. Furthermore, it comes in many different process flavors. Adoption by mainstream designers requires the availability of tools that let them evaluate...

    Provided By Democritus University of Thrace

  • White Papers // Oct 2006

    Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

    Power consumption is one of the major headaches, which should be tackled by the designers. Also, the parameters that affect significantly the performance and power are the Configurable Logic Blocks (CLBs) and the interconnection components. A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The main...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2008

    A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs

    Using new silicon technologies, increasing logic densities and clock frequencies on FPGAs (Field Programmable Gate Arrays) lead to rapid elevation in power density. Since the power consumption is a critical challenge for designing Three Dimensional (3D) Integrated Circuits (ICs), a novel temperature-aware Placement and Routing (P&R) algorithm targeting to 3D...

    Provided By Democritus University of Thrace

  • White Papers // Jul 2013

    A Platform-Independent Runtime Methodology for Mapping Multiple Applications Onto FPGAs Through Resource Virtualization

    Field Programmable Gate Arrays (FPGAs) promise a low power flexible alternative for implementing parallel applications. Compared to CPUs (Central Processing Units) and GPUs (Graphics Processing Units), they suffer from slow development cycles due to the high complexity of application development and hardware incompatibilities. Towards this direction, the authors propose a...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2015

    Design and Implementation of a Secure Mobile IP Architecture

    The increasing number of portable computers, combined with the requirement for non-stop connections to networks, makes the provision of Internet mobility important. Mobile IP defines protocols and procedures by which a mobile node can exchange packets, regardless of its current point-of-attachment to the Internet, and without changing its IP address....

    Provided By Democritus University of Thrace

  • White Papers // Jan 2010

    Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's

    In this paper, the authors present a design methodology and associated tool chain for efficient design of complex MPSoC architectures implemented using 3D-Stacked Integrated Circuit (3D-SIC). The proposed framework is based on a three step methodology that combines relatively accurate high-level, and two more accurate low-level prototyping tools. The high-level...

    Provided By Democritus University of Thrace

  • White Papers // Nov 2009

    A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations

    In this paper, the authors present a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA (Field Programmable Gate Array) implementation figures are given for various implementation parameters of...

    Provided By Democritus University of Thrace

  • White Papers // Jun 2012

    Framework for Performing Rapid Evaluation of 3D SoCs

    In recent years, the 3D IC (Integrated Circuit) has attracted increasing attention. Along with technology updates, there are several published works dealing with the 3D physical design problem. Among others, tools for partitioning, floor-plan, placement and routing for 3D architectures have been proposed. These approaches are based almost exclusively on...

    Provided By Democritus University of Thrace

  • White Papers // Sep 2012

    A Novel Prototyping and Evaluation Framework for NoC-based MPSoC

    In this paper, the authors present a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking test...

    Provided By Democritus University of Thrace

  • White Papers // Dec 2012

    An FPGA Implementation of the SURF Algorithm for the ExoMars Programme

    Achieving highly accurate feature extraction in a short period of time is very important for space applications based on computer vision algorithms, such as with the ExoMars programme of ESA (European Space Agency). The paper describes a HW/SW co-design scheme using FPGAs (Field Programmable Gate Arrays) to speed-up the SURF...

    Provided By Democritus University of Thrace

  • White Papers // Mar 2012

    The SPARTAN Project: FPGA-based Implementation of Computer Vision Algorithms Targeting to Space Applications

    The exploration of Mars is one of the main goals for both NASA and ESA, as confirmed by past and recent activities. Vision-based robotics applications have been widely studied in the last years. However, up to now solutions that have been proposed were affecting mostly software level. The SPARTAN project...

    Provided By Democritus University of Thrace

  • White Papers // Aug 2011

    A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

    Interconnection structures in FPGAs (Field Programmable Gate Arrays) increasingly contribute more to the delay and power consumption. Three-Dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have...

    Provided By Democritus University of Thrace

  • White Papers // Jan 2013

    A Framework for Performing Fault-Tolerant Placement Based on Genetic Algorithm

    Fault-tolerance is a crucial challenge for a number of application domains. Existing solutions to this problem are applied uniformly at the entire design imposing among others mentionable delay and power overheads. In this paper, the authors introduce a software-supported framework based on genetic algorithm for supporting fast application placement under...

    Provided By Democritus University of Thrace

  • White Papers // Nov 2012

    SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation

    Autonomous rover navigation is a challenging goal for space missions. One of the most critical tasks towards this direction affects the efficient implementation of computer vision algorithms. Apart from their increased computational complexity imposed by these algorithms, additional constraints are posed whenever they are employed for space missions. This paper...

    Provided By Democritus University of Thrace