European Design and Automation Association

Displaying 1-40 of 161 results

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Mar 2012

    Compositional System-Level Design Exploration With Planning of High-Level Synthesis

    The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration the authors present three main contributions: a concise library format for characterization and reuse...

    Provided By European Design and Automation Association

  • White Papers // Feb 2012

    Run-time Power-gating in Caches of GPUs for Leakage Energy Savings

    In this paper, the authors propose a novel micro-architectural technique for run-time power-gating caches of GPUs to save leakage energy. The L1 cache (private to a core) can be put in a low-leakage sleep mode when there are no ready threads to be scheduled, and the L2 cache can be...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints

    In this paper, the authors consider distributed real-time embedded systems in which confidentiality of the internal communication is critical. They present an approach to efficiently implement cryptographic algorithms by using hardware/software co-design techniques. The objective is to find the minimal hardware overhead and corresponding process mapping for encryption and decryption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Power Management of Multi-Core Chips: Challenges and Pitfalls

    Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, the authors examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that they pose is: How to ensure that such managed systems are \"Energy-secure\" and how to pursue pre-silicon...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    SAFER PATH: Security Architecture using Fragmented Execution and Replication for Protection Against Trojaned Hardware

    Ensuring electronic components are free from Hardware Trojans is a very difficult task. Research suggests that even the best pre- and post-deployment detection mechanisms will not discover all malicious inclusions, nor prevent them from being activated. For economic reasons electronic components are used regardless of the possible presence of such...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Predicting Best Design Trade-offs: A Case Study in Processor Customization

    Given the high level description of a task, many different hardware modules may be generated while meeting its behavioral requirements. The characteristics of the generated hardware can be tailored to favor energy efficiency, performance and accuracy or die area. The inherent trade-offs between such metrics need to be explored in...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Ultra Low Power Litho Friendly Local Assist Circuitry For Variability Resilient 8T SRAM

    Read-decoupled 8T SRAM cell offers a higher degree of variability resilience compared to 6T SRAM cell at the expense of an increased area overhead. This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems

    In this paper, the authors present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by Dynamic Voltage and Frequency Scaling (DVFS) methods in the presence of systematic and random variations. They show that maximum rejection for Process, Voltage and Temperature (PVT)...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    MAPG: Memory Access Power Gating

    In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this paper, the authors propose and model Memory Access Power Gating (MAPG), a...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

    Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Refinement of UML/MARTE Models for the Design of Networked Embedded Systems

    Network design in distributed embedded applications is a novel challenging task which requires the extraction of communication requirements from application specification and the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/ MARTE as specification front-end and repository of refined versions...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions

    Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection

    In this paper, the authors offer a framework which does not rely on a Golden IC (GIC) during Hardware Trojan (HT) detection. GIC is a Trojan-free IC which is required, in all existing HT frameworks, as a reference point to verify the responses obtained from an IC under authentication. However,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Towards Improving Simulation of Analog Circuits using Model Order Reduction

    Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation

    The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation

    In this paper, the authors propose a new envelope-following parallel transient analysis method for the general switching power converters. The new method first exploits the parallelisim in the envelope-following method and parallelize the Newton update solving part, which is the most computational expensive, in GPU platforms to boost the simulation...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    State-Based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture

    It has been one of the most fundamental challenges in architecture design to achieve high performance with low power while maintaining flexibility. Parallel architectures such as coarse-grained reconfigurable architecture, where multiple PEs are tightly coupled with each other, can be a viable solution to the problem. However, the PEs are...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures

    Reconfigurable systems represent as a suitable option to meet performance, power, and cost constraints that characterize the challenge of future supercomputing, provided that reconfiguration overhead is balanced with respect to computationally intensive workload. Resource run-time managers have been shown particularly effective for coordinating the usage of the hardware resources by...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems

    The need to improve the performance/energy ratio has caused a general trend towards increased heterogeneity in multi- and manycore systems, where general-purpose computing cores are complemented with energy-efficient special-purpose accelerators located either on or off-chip, as in, e.g., GPU-supported systems. However, this trend has also brought new, fundamental problems for...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design

    In this paper, the authors present component-based and aspect-oriented methodology and tool for designing and developing Real-Time Embedded Control Systems (RTECS). This methodology defines a component model for describing modular and reusable software to cope with the increasing complexity of embedded systems. It proposes an aspect-oriented approach to address explicitly...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Adaptive Approach for Online Fault Management in Many-Core Architectures

    In this paper, the authors present a dynamic scheduling solution to achieve fault tolerance in many-core architectures. Triple Modular Redundancy is applied on the multi-threaded application to dynamically mitigate the effects of both permanent and transient faults, and to identify and isolate damaged units. The approach targets the best performance,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation

    Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Exploring Pausible Clocking Based GALS Design for 40-nm System Integration

    Globally Asynchronous Locally Synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This paper explored the applications of pausible clocking scheme for area/power...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Static Analysis of Asynchronous Clock Domain Crossings

    Clock Domain Crossing (CDC) signals pose unique and challenging issues in complex designs with multiple asynchronous clocks running at frequencies as high as multiple giga hertz. Designers can no longer rely on ad hoc approaches to CDC analysis. This paper describes a methodical approach for static analysis of structural issues...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors

    Many leading CPU manufacturers today sell multi-core processors which leverage technology scaling to pack multiple processing units or cores in a single die. Modern multi-core processors use power management techniques such as Dynamic Voltage and Frequency Scaling (DVFS) and Clock Gating (CG) which cause the processor to operate in various...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Energy Efficient DRAM Subsystem for 3D integrated SoCs

    Energy efficiency is the key driver for the design optimization of System-on-Chips (SoCs) for mobile terminals (Smartphone's and tablets). 3D integration of heterogeneous dies based on TSV (through silicon via) technology enables stacking of multiple memory or logic layers and has the advantage of higher bandwidth at lower energy consumption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    On-Chip Source Synchronous Interface Timing Test Scheme with Calibration

    In this paper, the authors present an on-chip test circuit with a high resolution for testing source synchronous interface timing. Instead of a traditional strobe-scanning method, an on-chip delay measurement technique which detects the timing mismatches between data and clock paths is developed. Using a programmable pulse generator, the timing...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs

    FIR filters are widely used in Digital Signal Processing (DSP) applications due to their stability and linear-phase property. The Multiple Constant Multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital Finite Impulse...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Salvaging Chips with Caches beyond Repair

    Defect density and variabilities in values of parameters continue to grow with each new generation of nano-scale fabrication technology. In SRAMs, variabilities reduce yield and necessitate extensive interventions, such as the use of increasing numbers of spares to achieve acceptable yield. For most microprocessor chips, the number of SRAM bits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Flit-level Speedup Scheme For Network-on-Chips Using Self-Reconfigurable Bi-directional Channels

    In this paper, the authors propose a flit-level speedup scheme to enhance the Network-on-Chip (NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, their proposed flit-level speedup scheme also allows flits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs

    As one promising candidate for next-generation nonvolatile memory technologies, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. In this paper, the authors reveal an important fact that has been neglected in STT-RAM designs...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Comparative Analysis of SRAM Memories Used as PUF Primitives

    In this paper, the authors present the results of their investigations into the reliability and uniqueness of Static Random Access Memories (SRAMs) in different technology nodes when used as a Physically Unclonable Function (PUF). The comparative analysis that can be found in this publication is the first ever of its...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures

    Processor architectures with Fine-Grained Reconfigurable Accelerators (FGRAs) allow for a high degree of adaptivity to address varying application requirements. When processing computation intensive kernels, multiple FGRAs may be used to execute a complex function. In order to exploit the adaptivity of a fine-grained reconfigurable fabric, a runtime system should decide...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Congestion-Aware Scheduling for NoC-based Reconfigurable Systems

    Network-on-Chip (NoC) is becoming a promising communication architecture in place of dedicated interconnections and shared buses for embedded systems. Nevertheless, it has also created new design issue such as communication congestion and power consumption. A major factor leading to communication congestion is mapping of application tasks to NoC. Latency, throughput,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations

    In this paper, the authors offer a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems

    In this paper, the authors target at an embedded system with Phase Change Memory (PCM) and NAND flash memory. Although PCM is a promising main memory alternative and is recently introduced to embedded system designs, its endurance keeps drifting down and greatly limits the lifetime of the whole system. Therefore,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices

    Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper, the authors propose a novel common-source-line array architecture, which uses a shared source-line along the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Fast, Source-synchronous Ring-based Network-on-Chip Design

    Most Network-on-Chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, the authors present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches

    Asynchronous on-chip networks are good candidates for multi-core applications requiring low-power consumption. Asynchronous Spatial Division Multiplexing (SDM) routers provide better throughput with lower area overhead than asynchronous virtual channel routers; however, the area overhead of SDM routers is still significant due to their high-radix central switches. A new 2-stage Clos...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Out-of-Order Parallel Simulation for ESL Design

    At the Electronic System Level (ESL), design validation often relies on Discrete Event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Approximating Checkers for Simulation Acceleration

    Simulation-based functional verification is the key validation methodology the industry. The performance of logic simulators, however, is not sufficient to attain acceptable verification coverage on large industrial designs within the time-frame available. Acceleration platforms are a valuable addition to the verification effort in that they can provide much higher coverage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers

    Many companies deploy multiple data centers across the globe to satisfy the dramatically increased computational demand. Wide area connectivity between such geographically distributed data centers has an important role to ensure both the quality of service, and, as bandwidths increase to 100Gbps and beyond, as an efficient way to dynamically...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer

    Dynamic Frequency and Voltage Scaling (DVFS) techniques have been widely used for meeting energy constraints. Single-chip many-core systems bring new challenges owing to the large number of operating points and the shift to Message Passing Interface (MPI) from shared memory communication. DVFS, however, has been mostly studied on single-chip systems...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Task Implementation of Synchronous Finite State Machines

    Model-based design of embedded control systems using Synchronous Reactive (SR) models is among the best practices for software development in the automotive and aeronautics industry. SR models allow to formally verify the correctness of the design and to automatically generate the implementation code. This improves productivity and, more importantly, can...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Hazard Driven Test Generation for SMT Processors

    Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multi-Threaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems

    Efficiently managing the parallel execution of various application tasks onto a heterogeneous multi-core system consisting of a combination of processors and accelerators is a difficult task due to the complex system architecture. The management of reconfigurable multi-core systems which exploit dynamic and partial reconfiguration in order to, e.g. increase the...

    Provided By European Design and Automation Association

  • White Papers // Feb 2012

    Run-time Power-gating in Caches of GPUs for Leakage Energy Savings

    In this paper, the authors propose a novel micro-architectural technique for run-time power-gating caches of GPUs to save leakage energy. The L1 cache (private to a core) can be put in a low-leakage sleep mode when there are no ready threads to be scheduled, and the L2 cache can be...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis

    System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints

    In this paper, the authors consider distributed real-time embedded systems in which confidentiality of the internal communication is critical. They present an approach to efficiently implement cryptographic algorithms by using hardware/software co-design techniques. The objective is to find the minimal hardware overhead and corresponding process mapping for encryption and decryption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Power Management of Multi-Core Chips: Challenges and Pitfalls

    Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, the authors examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that they pose is: How to ensure that such managed systems are \"Energy-secure\" and how to pursue pre-silicon...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads

    Future computing clusters will prevalently run parallel workloads to take advantage of the increasing number of cores on chips. In tandem, there is a growing need to reduce energy consumption of computing. One promising method for improving energy efficiency is co-scheduling applications on compute nodes. Efficient consolidation for parallel workloads...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    SAFER PATH: Security Architecture using Fragmented Execution and Replication for Protection Against Trojaned Hardware

    Ensuring electronic components are free from Hardware Trojans is a very difficult task. Research suggests that even the best pre- and post-deployment detection mechanisms will not discover all malicious inclusions, nor prevent them from being activated. For economic reasons electronic components are used regardless of the possible presence of such...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Predicting Best Design Trade-offs: A Case Study in Processor Customization

    Given the high level description of a task, many different hardware modules may be generated while meeting its behavioral requirements. The characteristics of the generated hardware can be tailored to favor energy efficiency, performance and accuracy or die area. The inherent trade-offs between such metrics need to be explored in...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Ultra Low Power Litho Friendly Local Assist Circuitry For Variability Resilient 8T SRAM

    Read-decoupled 8T SRAM cell offers a higher degree of variability resilience compared to 6T SRAM cell at the expense of an increased area overhead. This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems

    In this paper, the authors present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by Dynamic Voltage and Frequency Scaling (DVFS) methods in the presence of systematic and random variations. They show that maximum rejection for Process, Voltage and Temperature (PVT)...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    MAPG: Memory Access Power Gating

    In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this paper, the authors propose and model Memory Access Power Gating (MAPG), a...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

    Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Refinement of UML/MARTE Models for the Design of Networked Embedded Systems

    Network design in distributed embedded applications is a novel challenging task which requires the extraction of communication requirements from application specification and the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/ MARTE as specification front-end and repository of refined versions...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions

    Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage...

    Provided By European Design and Automation Association

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications

    Multi-Processor Systems-on-Chips (MPSoCs), composed of several processing elements and on-chip memories, have become the standard for implementing embedded systems. Thanks to the presence of multiple processing units, these systems potentially allow a better management of periodic workloads and can react faster to external, aperiodic events. This paper presents the implementation...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Application-Based EDF Scheduler for OSEK/VDX

    Earliest Deadline First (EDF) scheduling performs processor utilization up to 100 percent and improved robustness in overload situations. However, most automotive applications are running under static priority policy. Because of this, the standard operating system in the automotive industry, OSEK/VDX, just supports priority scheduling. This paper describes an EDF scheduler...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Efficient Algorithm for Free Resources Management on the FPGA

    Finding the available empty space for arrival tasks on FPGAs with runtime partially reconfigurable abilities is the most time consuming phase in on-line placement algorithms. Naturally, this phase has the highest impact on the overall system performance. In this paper, the authors present a new algorithm which is used to...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Specification and Design Considerations for Reliable Embedded Systems

    In this paper, the authors introduce a novel representation as a means to consider both permanent and temporal errors in order to increase the overall reliability of an embedded system. The deployment of embedded systems in safety critical applications, e.g. in the automotive domain, demands that the fundamental set of...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Synthesis of Fault-Tolerant Embedded Systems

    In this paper, the authors address the issue of design optimization for fault-tolerant hard real-time systems. In particular, their focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Memory Technology for Extended Large-Scale Integration in Future Electronics Applications

    Extending 2-D planar topologies in Integrated Circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length, with associated improvements in cost, and delay and energy consumption, while also providing an opportunity to integrate disparate technologies. Such advances are very much technology...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis

    In this paper, the authors introduce a new formal model for specifying control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG) is capable of capturing concurrency and choice in a system's behavior in a compact and efficient way. A problem of CPOG...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Operating System Controlled Processor-Memory Bus Encryption

    Unencrypted data appearing on the processor - memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Although on-chip bus encryption hardware can solve this problem, it requires hardware redesign or increases processor cost. Application redesign to prevent sensitive data from...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Instruction Cache Energy Saving Through Compiler Way-Placement

    Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to ad-dress this issue involve predicting or memoizing the correct way to access. However, they also require significant hard-ware storage which negates much of the...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications

    Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels....

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Automatic Selection of Application-Specific Reconfigurable Processor Extensions

    In this paper, the authors present a new method for automatic selection of application-specific processor extensions and shows how applications are scheduled on these new reconfigurable architectures. The extensions are implemented as specialized sequential or parallel instructions. They correspond to identified most frequently occurring computational patterns or other interesting patterns...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications

    Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high throughput in a cost-efficient way. However, the design of such systems poses various challenges due to the complexities posed by the applications themselves as well as the heterogeneous nature of...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    User-Aware Dynamic Task Allocation in Networks-on-Chip

    In this paper, the authors propose a run-time strategy for allocating the application tasks to platform resources in homogeneous Network-on-Chips (NoCs). As novel contribution, they incorporate the user behavior information in the resource allocation process; this allows system to better respond to real-time changes and adapt dynamically to user needs....

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures

    The authors present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the router in a NoC) used to implement logical channels multiplexed across the physical channel in a router output port for QoS...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication

    3D stacked memory is being adopted as a promising solution to offer high bandwidth and low latency in memory access. Compared with the on-chip network design with conventional off-chip memory, it gives a new problem of minimizing communication conflicts since multiple concurrent high bandwidth data transfers will flow through the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection

    In this paper, the authors offer a framework which does not rely on a Golden IC (GIC) during Hardware Trojan (HT) detection. GIC is a Trojan-free IC which is required, in all existing HT frameworks, as a reference point to verify the responses obtained from an IC under authentication. However,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Towards Improving Simulation of Analog Circuits using Model Order Reduction

    Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation

    The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation

    In this paper, the authors propose a new envelope-following parallel transient analysis method for the general switching power converters. The new method first exploits the parallelisim in the envelope-following method and parallelize the Newton update solving part, which is the most computational expensive, in GPU platforms to boost the simulation...

    Provided By European Design and Automation Association