European Design and Automation Association

Displaying 1-40 of 159 results

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Mar 2012

    Compositional System-Level Design Exploration With Planning of High-Level Synthesis

    The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration the authors present three main contributions: a concise library format for characterization and reuse...

    Provided By European Design and Automation Association

  • White Papers // Feb 2012

    Run-time Power-gating in Caches of GPUs for Leakage Energy Savings

    In this paper, the authors propose a novel micro-architectural technique for run-time power-gating caches of GPUs to save leakage energy. The L1 cache (private to a core) can be put in a low-leakage sleep mode when there are no ready threads to be scheduled, and the L2 cache can be...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures

    Reconfigurable systems represent as a suitable option to meet performance, power, and cost constraints that characterize the challenge of future supercomputing, provided that reconfiguration overhead is balanced with respect to computationally intensive workload. Resource run-time managers have been shown particularly effective for coordinating the usage of the hardware resources by...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems

    The need to improve the performance/energy ratio has caused a general trend towards increased heterogeneity in multi- and manycore systems, where general-purpose computing cores are complemented with energy-efficient special-purpose accelerators located either on or off-chip, as in, e.g., GPU-supported systems. However, this trend has also brought new, fundamental problems for...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design

    In this paper, the authors present component-based and aspect-oriented methodology and tool for designing and developing Real-Time Embedded Control Systems (RTECS). This methodology defines a component model for describing modular and reusable software to cope with the increasing complexity of embedded systems. It proposes an aspect-oriented approach to address explicitly...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Adaptive Approach for Online Fault Management in Many-Core Architectures

    In this paper, the authors present a dynamic scheduling solution to achieve fault tolerance in many-core architectures. Triple Modular Redundancy is applied on the multi-threaded application to dynamically mitigate the effects of both permanent and transient faults, and to identify and isolate damaged units. The approach targets the best performance,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation

    Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems

    In this paper, the authors target at an embedded system with Phase Change Memory (PCM) and NAND flash memory. Although PCM is a promising main memory alternative and is recently introduced to embedded system designs, its endurance keeps drifting down and greatly limits the lifetime of the whole system. Therefore,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices

    Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper, the authors propose a novel common-source-line array architecture, which uses a shared source-line along the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Fast, Source-synchronous Ring-based Network-on-Chip Design

    Most Network-on-Chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, the authors present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches

    Asynchronous on-chip networks are good candidates for multi-core applications requiring low-power consumption. Asynchronous Spatial Division Multiplexing (SDM) routers provide better throughput with lower area overhead than asynchronous virtual channel routers; however, the area overhead of SDM routers is still significant due to their high-radix central switches. A new 2-stage Clos...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Bloom Filter-Based Dynamic Wear Leveling for Phase-Change RAM

    Phase Change Memory (PCM) is a promising candidate of emerging memory technology to complement or replace existing DRAM and NAND Flash memory. A key drawback of PCMs is limited write endurance. To address this problem, several static wear-leveling methods that change logical to physical address mapping periodically have been proposed....

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors

    Non-volatile processor has become an emerging topic in recent years due to its zero standby power, resilience to power failures and instant on feature. This paper first demonstrated a fabricated nonvolatile 8051-compatible processor design, which indicates the ferroelectric nonvolatile version leads to over 90% area overhead compared with the volatile...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Network-on-Chip-Based Turbo/LDPC Decoder Architecture

    The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    SAFER PATH: Security Architecture using Fragmented Execution and Replication for Protection Against Trojaned Hardware

    Ensuring electronic components are free from Hardware Trojans is a very difficult task. Research suggests that even the best pre- and post-deployment detection mechanisms will not discover all malicious inclusions, nor prevent them from being activated. For economic reasons electronic components are used regardless of the possible presence of such...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Predicting Best Design Trade-offs: A Case Study in Processor Customization

    Given the high level description of a task, many different hardware modules may be generated while meeting its behavioral requirements. The characteristics of the generated hardware can be tailored to favor energy efficiency, performance and accuracy or die area. The inherent trade-offs between such metrics need to be explored in...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Ultra Low Power Litho Friendly Local Assist Circuitry For Variability Resilient 8T SRAM

    Read-decoupled 8T SRAM cell offers a higher degree of variability resilience compared to 6T SRAM cell at the expense of an increased area overhead. This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems

    In this paper, the authors present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by Dynamic Voltage and Frequency Scaling (DVFS) methods in the presence of systematic and random variations. They show that maximum rejection for Process, Voltage and Temperature (PVT)...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    MAPG: Memory Access Power Gating

    In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this paper, the authors propose and model Memory Access Power Gating (MAPG), a...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

    Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Refinement of UML/MARTE Models for the Design of Networked Embedded Systems

    Network design in distributed embedded applications is a novel challenging task which requires the extraction of communication requirements from application specification and the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/ MARTE as specification front-end and repository of refined versions...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions

    Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Exploring Pausible Clocking Based GALS Design for 40-nm System Integration

    Globally Asynchronous Locally Synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This paper explored the applications of pausible clocking scheme for area/power...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Static Analysis of Asynchronous Clock Domain Crossings

    Clock Domain Crossing (CDC) signals pose unique and challenging issues in complex designs with multiple asynchronous clocks running at frequencies as high as multiple giga hertz. Designers can no longer rely on ad hoc approaches to CDC analysis. This paper describes a methodical approach for static analysis of structural issues...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors

    Many leading CPU manufacturers today sell multi-core processors which leverage technology scaling to pack multiple processing units or cores in a single die. Modern multi-core processors use power management techniques such as Dynamic Voltage and Frequency Scaling (DVFS) and Clock Gating (CG) which cause the processor to operate in various...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Selective Flexibility: Breaking the Rigidity of Datapath Merging

    Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. The authors merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design

    Embedded systems based on FPGA (Field-Programmable Gate Arrays) must exhibit more performance for new applications. However, no high-performance superscalar soft processor is available on the FPGA, because the superscalar architecture is not suitable for FPGAs. High-performance superscalar processors execute instructions out-of-order and it is necessary to re-order instructions after execution....

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures

    Processor architectures with Fine-Grained Reconfigurable Accelerators (FGRAs) allow for a high degree of adaptivity to address varying application requirements. When processing computation intensive kernels, multiple FGRAs may be used to execute a complex function. In order to exploit the adaptivity of a fine-grained reconfigurable fabric, a runtime system should decide...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Congestion-Aware Scheduling for NoC-based Reconfigurable Systems

    Network-on-Chip (NoC) is becoming a promising communication architecture in place of dedicated interconnections and shared buses for embedded systems. Nevertheless, it has also created new design issue such as communication congestion and power consumption. A major factor leading to communication congestion is mapping of application tasks to NoC. Latency, throughput,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations

    In this paper, the authors offer a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Energy Efficient DRAM Subsystem for 3D integrated SoCs

    Energy efficiency is the key driver for the design optimization of System-on-Chips (SoCs) for mobile terminals (Smartphone's and tablets). 3D integration of heterogeneous dies based on TSV (through silicon via) technology enables stacking of multiple memory or logic layers and has the advantage of higher bandwidth at lower energy consumption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    On-Chip Source Synchronous Interface Timing Test Scheme with Calibration

    In this paper, the authors present an on-chip test circuit with a high resolution for testing source synchronous interface timing. Instead of a traditional strobe-scanning method, an on-chip delay measurement technique which detects the timing mismatches between data and clock paths is developed. Using a programmable pulse generator, the timing...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs

    FIR filters are widely used in Digital Signal Processing (DSP) applications due to their stability and linear-phase property. The Multiple Constant Multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital Finite Impulse...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Salvaging Chips with Caches beyond Repair

    Defect density and variabilities in values of parameters continue to grow with each new generation of nano-scale fabrication technology. In SRAMs, variabilities reduce yield and necessitate extensive interventions, such as the use of increasing numbers of spares to achieve acceptable yield. For most microprocessor chips, the number of SRAM bits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Flit-level Speedup Scheme For Network-on-Chips Using Self-Reconfigurable Bi-directional Channels

    In this paper, the authors propose a flit-level speedup scheme to enhance the Network-on-Chip (NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, their proposed flit-level speedup scheme also allows flits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs

    As one promising candidate for next-generation nonvolatile memory technologies, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. In this paper, the authors reveal an important fact that has been neglected in STT-RAM designs...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Comparative Analysis of SRAM Memories Used as PUF Primitives

    In this paper, the authors present the results of their investigations into the reliability and uniqueness of Static Random Access Memories (SRAMs) in different technology nodes when used as a Physically Unclonable Function (PUF). The comparative analysis that can be found in this publication is the first ever of its...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection

    In this paper, the authors offer a framework which does not rely on a Golden IC (GIC) during Hardware Trojan (HT) detection. GIC is a Trojan-free IC which is required, in all existing HT frameworks, as a reference point to verify the responses obtained from an IC under authentication. However,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Towards Improving Simulation of Analog Circuits using Model Order Reduction

    Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system,...

    Provided By European Design and Automation Association

  • White Papers // Apr 2011

    Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers

    The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation efficiency of competing hash candidates. However, such benchmarks test the algorithm in an ideal setting, and they ignore the effects of system integration. In...

    Provided By European Design and Automation Association

  • White Papers // Jan 2011

    Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories

    Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties, they are prone to wear-out due to excessive write operations. Because wear-out is an important phenomenon, a number of endurance management schemes have been proposed....

    Provided By European Design and Automation Association

  • White Papers // Feb 2010

    pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems

    Parallel programming techniques have become one of the great challenges in the transition from single-core to multicore architectures. In this paper, the authors investigate the parallelization of the Montgomery multiplication, a very common and timeconsuming primitive in public-key cryptography. A scalable parallel programming scheme, called pSHS, is presented to map...

    Provided By European Design and Automation Association

  • White Papers // Feb 2010

    Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC - A Case Study

    In this paper, the authors examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. They present several design choices and focus on the power optimization of the NoC while achieving the required performance. They design steps include module mapping and allocation of...

    Provided By European Design and Automation Association

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Mar 2012

    Compositional System-Level Design Exploration With Planning of High-Level Synthesis

    The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration the authors present three main contributions: a concise library format for characterization and reuse...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    Architectures and Modeling of Predictable Memory Controllers for Improved System Integration

    Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with real-time requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified together, resulting in...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, the authors suggest to partition a Network-on-Chip (NoC) based system into smaller sub-systems...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    Optimal Scheduling of Switched FlexRay Networks

    This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent star coupler, called a switch, to temporarily decouple network branches, thereby increasing the effective network bandwidth. Although scheduling for basic FlexRay...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    DRAM Selection and Configuration for Real-Time Mobile Systems

    The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both real-time and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    Memory-Map Selection for Firm Real-Time SDRAM Controllers

    A modern real-time embedded system must support multiple concurrently running applications. To reduce costs, critical SoC components like SDRAM memories are often shared between applications with a variety of firm real-time requirements. To guarantee that the system works as intended, the memory controller must be configured such that all the...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

    Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC implementations have been presented in the literature, some of them having mature tool-flows and ecosystems. The main differentiating factor between the various implementations are the services...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthread

    Multicore shared-memory multiprocessors now rule the desktop and server markets, and are poised to dominate embedded systems. Multicore shared-memory architectures are becoming prevalent and bring many programming challenges. Among the biggest are data races: accesses to shared resources that make a program's behavior depend on scheduling decisions beyond its control....

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    EzRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis

    In this paper, the authors introduce the ezRealtime project, which relies on the Time Petri Net (TPN) formalism and defines a Domain-Specific Modeling (DSM) tool to provide an easy-to-use environment for specifying Embedded Hard Real-Time (EHRT) systems and for synthesizing timely and predictable scheduled C code. Therefore, this paper presents...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols

    Processors with multiple cores and complex cache coherence protocols are widely employed to improve the overall performance. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. In this paper, the authors propose...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Generating Instruction Streams Using Abstract CSP

    One of the challenges that processor level stimuli generators are facing are the need to generate stimuli that exercise microarchitectural mechanisms deep inside the verified processor. These scenarios require specific relations between the instructions participating in them. The authors present a new approach for processor-level scenario generation. The approach is...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture

    Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the Instruction Set Architecture (ISA) can be adapted to increase performance or...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    TagTM - Accelerating STMs With Hardware Tags for Fast Meta-Data Access

    The industry shift towards Chip Multi-Processors (CMPs) has put many researchers to study new techniques which would make parallel programming easier. In this paper, the authors introduce TagTM, a Software Transactional Memory (STM) system augmented with a new hardware mechanism that they call GTags. GTags are new hardware cache coherent...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization

    With the constant scaling of Silicon technologies the reduction in leakage power has become one of the main challenges of modern Integrated Circuit (IC) design. In today's Systems-On-Chip (SOC) very often most of the chip area is taken by embedded SRAM, which leads in some cases to the leakage power...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Post-Synthesis Leakage Power Minimization

    For modern processes leakage power is almost comparable to the dynamic power even when the device is in the active mode. Efforts to mitigate this problem have resulted in multi-threshold voltage transistor implementations. The authors developed a new post-synthesis algorithm that minimizes leakage power while strictly preserving the delay constraint....

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores

    Several recent many-core accelerators have been architected as fabrics of tightly-coupled shared memory clusters. A hierarchical interconnection system is used - with a crossbar-like medium inside each cluster and a Network-on-Chip (NoC) at the global level - which make memory operations non-uniform. Nested parallelism represents a powerful programming abstraction for...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Divide and Conquer Based Distributed Run-Time Mapping Methodology for Many-Core Platforms

    Real-time applications are raising the challenge of unpredictability. This is an extremely difficult problem in the context of modern, dynamic, multiprocessor platforms which, while providing potentially high performance, make the task of timing prediction extremely difficult. In this paper, the authors present a flexible distributed run-time application mapping framework for...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks

    In the recent years, commodity solid-state disks have started adopting powerful controllers and implemented page-level mapping for flash management. However, many of these models still use primitive garbage-collection algorithms, because prior approaches do not scale up with the dramatic increase of flash capacity. This study introduces Dual Greedy for garbage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Out-of-Order Parallel Simulation for ESL Design

    At the Electronic System Level (ESL), design validation often relies on Discrete Event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    TinyTimber, Reactive Objects in C for Real-Time Embedded Systems

    Embedded systems are often operating under hard real-time constraints. Such systems are naturally described as time-bound reactions to external events, a point of view made manifest in the high-level programming and systems modeling language Timber. In this paper, the authors demonstrate how the Timber semantics for parallel reactive objects translates...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications

    In this paper, the authors evaluate task allocation strategies based on bin-packing algorithms in the context of Multi-Processor Systems-on-Chip (MPSoCs) with task migration capabilities, running soft real-time applications. The task migration model assumes that the whole code and data of the tasks are transferred from an origin node to the...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Developing Mesochronous Synchronizers to Enable 3D NoCs

    The Network-on-Chip (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The next challenge is to use NoCs as the backbones of the upcoming generation of 3D chips, assembled by stacking multiple silicon layers. Multiple technical issues have to be...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Memory Organization with Multi-Pattern Parallel Accesses

    The authors propose an interleaved memory organization supporting multi-pattern parallel accesses in Two-Dimensional (2D) addressing space. Their proposal targets computing systems with high memory bandwidth demands such as vector processors, multimedia accelerators, etc. They substantially extend prior research on interleaved memory organizations introducing 2D-strided accesses along with additional parameters, which...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches

    Cache-Content-Duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different tag. Caches aware of content-duplication can have lower miss rates by allowing only blocks with unique content...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Magellan: A Search and Machine Learning-Based Framework for Fast Multi-Core Design Space Exploration and Optimization

    In this paper, the authors treat multi-core processor design space exploration as an application-driven machine learning problem. They develop two machine learning-based techniques for efficiently exploring the processor design space. They observe that these techniques result in multi-core processors whose performance is comparable (within 1%) to a processor design that...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    GMDS: Hardware Implementation of Novel Real Output Queuing Architecture

    In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (Gigabit MultiDrop Switch) and its main features are the switch...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography

    Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, the authors propose a low overhead...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    IFill: An Impact-Oriented X-Filling Method for Shift-And Capture-Power Reduction in At-Speed Scan-Based Testing

    In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, the authors present an X-filling technique that can decrease both...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

    Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Video Processing Requirements on SoC Infrastructures

    Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large storage capacity and high bandwidth while data accesses can be irregular. The System-on-Chip (SoC) architectures used for implementing these applications typically contain a heterogeneous collection of processing elements and...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    A Design-for-Diagnosis Technique for SRAM Write Drivers

    Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information of fault localization....

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications

    Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high throughput in a cost-efficient way. However, the design of such systems poses various challenges due to the complexities posed by the applications themselves as well as the heterogeneous nature of...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    User-Aware Dynamic Task Allocation in Networks-on-Chip

    In this paper, the authors propose a run-time strategy for allocating the application tasks to platform resources in homogeneous Network-on-Chips (NoCs). As novel contribution, they incorporate the user behavior information in the resource allocation process; this allows system to better respond to real-time changes and adapt dynamically to user needs....

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures

    The authors present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the router in a NoC) used to implement logical channels multiplexed across the physical channel in a router output port for QoS...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication

    3D stacked memory is being adopted as a promising solution to offer high bandwidth and low latency in memory access. Compared with the on-chip network design with conventional off-chip memory, it gives a new problem of minimizing communication conflicts since multiple concurrent high bandwidth data transfers will flow through the...

    Provided By European Design and Automation Association