European Design and Automation Association

Displaying 1-40 of 161 results

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Mar 2012

    Compositional System-Level Design Exploration With Planning of High-Level Synthesis

    The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration the authors present three main contributions: a concise library format for characterization and reuse...

    Provided By European Design and Automation Association

  • White Papers // Feb 2012

    Run-time Power-gating in Caches of GPUs for Leakage Energy Savings

    In this paper, the authors propose a novel micro-architectural technique for run-time power-gating caches of GPUs to save leakage energy. The L1 cache (private to a core) can be put in a low-leakage sleep mode when there are no ready threads to be scheduled, and the L2 cache can be...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Power Management of Multi-Core Chips: Challenges and Pitfalls

    Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, the authors examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that they pose is: How to ensure that such managed systems are \"Energy-secure\" and how to pursue pre-silicon...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints

    In this paper, the authors consider distributed real-time embedded systems in which confidentiality of the internal communication is critical. They present an approach to efficiently implement cryptographic algorithms by using hardware/software co-design techniques. The objective is to find the minimal hardware overhead and corresponding process mapping for encryption and decryption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems

    In this paper, the authors present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by Dynamic Voltage and Frequency Scaling (DVFS) methods in the presence of systematic and random variations. They show that maximum rejection for Process, Voltage and Temperature (PVT)...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Ultra Low Power Litho Friendly Local Assist Circuitry For Variability Resilient 8T SRAM

    Read-decoupled 8T SRAM cell offers a higher degree of variability resilience compared to 6T SRAM cell at the expense of an increased area overhead. This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Predicting Best Design Trade-offs: A Case Study in Processor Customization

    Given the high level description of a task, many different hardware modules may be generated while meeting its behavioral requirements. The characteristics of the generated hardware can be tailored to favor energy efficiency, performance and accuracy or die area. The inherent trade-offs between such metrics need to be explored in...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    SAFER PATH: Security Architecture using Fragmented Execution and Replication for Protection Against Trojaned Hardware

    Ensuring electronic components are free from Hardware Trojans is a very difficult task. Research suggests that even the best pre- and post-deployment detection mechanisms will not discover all malicious inclusions, nor prevent them from being activated. For economic reasons electronic components are used regardless of the possible presence of such...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions

    Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Refinement of UML/MARTE Models for the Design of Networked Embedded Systems

    Network design in distributed embedded applications is a novel challenging task which requires the extraction of communication requirements from application specification and the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/ MARTE as specification front-end and repository of refined versions...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

    Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    MAPG: Memory Access Power Gating

    In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this paper, the authors propose and model Memory Access Power Gating (MAPG), a...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations

    In this paper, the authors offer a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Congestion-Aware Scheduling for NoC-based Reconfigurable Systems

    Network-on-Chip (NoC) is becoming a promising communication architecture in place of dedicated interconnections and shared buses for embedded systems. Nevertheless, it has also created new design issue such as communication congestion and power consumption. A major factor leading to communication congestion is mapping of application tasks to NoC. Latency, throughput,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation

    In this paper, the authors propose a new envelope-following parallel transient analysis method for the general switching power converters. The new method first exploits the parallelisim in the envelope-following method and parallelize the Newton update solving part, which is the most computational expensive, in GPU platforms to boost the simulation...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation

    The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures

    Reconfigurable systems represent as a suitable option to meet performance, power, and cost constraints that characterize the challenge of future supercomputing, provided that reconfiguration overhead is balanced with respect to computationally intensive workload. Resource run-time managers have been shown particularly effective for coordinating the usage of the hardware resources by...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    State-Based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture

    It has been one of the most fundamental challenges in architecture design to achieve high performance with low power while maintaining flexibility. Parallel architectures such as coarse-grained reconfigurable architecture, where multiple PEs are tightly coupled with each other, can be a viable solution to the problem. However, the PEs are...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Comparative Analysis of SRAM Memories Used as PUF Primitives

    In this paper, the authors present the results of their investigations into the reliability and uniqueness of Static Random Access Memories (SRAMs) in different technology nodes when used as a Physically Unclonable Function (PUF). The comparative analysis that can be found in this publication is the first ever of its...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs

    As one promising candidate for next-generation nonvolatile memory technologies, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. In this paper, the authors reveal an important fact that has been neglected in STT-RAM designs...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Towards Improving Simulation of Analog Circuits using Model Order Reduction

    Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection

    In this paper, the authors offer a framework which does not rely on a Golden IC (GIC) during Hardware Trojan (HT) detection. GIC is a Trojan-free IC which is required, in all existing HT frameworks, as a reference point to verify the responses obtained from an IC under authentication. However,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs

    FIR filters are widely used in Digital Signal Processing (DSP) applications due to their stability and linear-phase property. The Multiple Constant Multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital Finite Impulse...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    On-Chip Source Synchronous Interface Timing Test Scheme with Calibration

    In this paper, the authors present an on-chip test circuit with a high resolution for testing source synchronous interface timing. Instead of a traditional strobe-scanning method, an on-chip delay measurement technique which detects the timing mismatches between data and clock paths is developed. Using a programmable pulse generator, the timing...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Flit-level Speedup Scheme For Network-on-Chips Using Self-Reconfigurable Bi-directional Channels

    In this paper, the authors propose a flit-level speedup scheme to enhance the Network-on-Chip (NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, their proposed flit-level speedup scheme also allows flits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Salvaging Chips with Caches beyond Repair

    Defect density and variabilities in values of parameters continue to grow with each new generation of nano-scale fabrication technology. In SRAMs, variabilities reduce yield and necessitate extensive interventions, such as the use of increasing numbers of spares to achieve acceptable yield. For most microprocessor chips, the number of SRAM bits...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Static Analysis of Asynchronous Clock Domain Crossings

    Clock Domain Crossing (CDC) signals pose unique and challenging issues in complex designs with multiple asynchronous clocks running at frequencies as high as multiple giga hertz. Designers can no longer rely on ad hoc approaches to CDC analysis. This paper describes a methodical approach for static analysis of structural issues...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Exploring Pausible Clocking Based GALS Design for 40-nm System Integration

    Globally Asynchronous Locally Synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This paper explored the applications of pausible clocking scheme for area/power...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Energy Efficient DRAM Subsystem for 3D integrated SoCs

    Energy efficiency is the key driver for the design optimization of System-on-Chips (SoCs) for mobile terminals (Smartphone's and tablets). 3D integration of heterogeneous dies based on TSV (through silicon via) technology enables stacking of multiple memory or logic layers and has the advantage of higher bandwidth at lower energy consumption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors

    Many leading CPU manufacturers today sell multi-core processors which leverage technology scaling to pack multiple processing units or cores in a single die. Modern multi-core processors use power management techniques such as Dynamic Voltage and Frequency Scaling (DVFS) and Clock Gating (CG) which cause the processor to operate in various...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Selective Flexibility: Breaking the Rigidity of Datapath Merging

    Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. The authors merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design

    Embedded systems based on FPGA (Field-Programmable Gate Arrays) must exhibit more performance for new applications. However, no high-performance superscalar soft processor is available on the FPGA, because the superscalar architecture is not suitable for FPGAs. High-performance superscalar processors execute instructions out-of-order and it is necessary to re-order instructions after execution....

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures

    Processor architectures with Fine-Grained Reconfigurable Accelerators (FGRAs) allow for a high degree of adaptivity to address varying application requirements. When processing computation intensive kernels, multiple FGRAs may be used to execute a complex function. In order to exploit the adaptivity of a fine-grained reconfigurable fabric, a runtime system should decide...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Bloom Filter-Based Dynamic Wear Leveling for Phase-Change RAM

    Phase Change Memory (PCM) is a promising candidate of emerging memory technology to complement or replace existing DRAM and NAND Flash memory. A key drawback of PCMs is limited write endurance. To address this problem, several static wear-leveling methods that change logical to physical address mapping periodically have been proposed....

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors

    Non-volatile processor has become an emerging topic in recent years due to its zero standby power, resilience to power failures and instant on feature. This paper first demonstrated a fabricated nonvolatile 8051-compatible processor design, which indicates the ferroelectric nonvolatile version leads to over 90% area overhead compared with the volatile...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Network-on-Chip-Based Turbo/LDPC Decoder Architecture

    The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems

    In this paper, the authors target at an embedded system with Phase Change Memory (PCM) and NAND flash memory. Although PCM is a promising main memory alternative and is recently introduced to embedded system designs, its endurance keeps drifting down and greatly limits the lifetime of the whole system. Therefore,...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices

    Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper, the authors propose a novel common-source-line array architecture, which uses a shared source-line along the...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    A Fast, Source-synchronous Ring-based Network-on-Chip Design

    Most Network-on-Chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, the authors present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that...

    Provided By European Design and Automation Association

  • White Papers // Mar 2009

    Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage

    Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware, and not on the system integration into SoC architecture. The authors study the impact of the communication link between CPU and coprocessor...

    Provided By European Design and Automation Association

  • White Papers // Jan 2011

    Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories

    Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties, they are prone to wear-out due to excessive write operations. Because wear-out is an important phenomenon, a number of endurance management schemes have been proposed....

    Provided By European Design and Automation Association

  • White Papers // Feb 2010

    pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems

    Parallel programming techniques have become one of the great challenges in the transition from single-core to multicore architectures. In this paper, the authors investigate the parallelization of the Montgomery multiplication, a very common and timeconsuming primitive in public-key cryptography. A scalable parallel programming scheme, called pSHS, is presented to map...

    Provided By European Design and Automation Association

  • White Papers // Apr 2011

    Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers

    The SHA-3 competition organized by NIST has triggered significant efforts in performance evaluation of cryptographic hardware and software. These benchmarks are used to compare the implementation efficiency of competing hash candidates. However, such benchmarks test the algorithm in an ideal setting, and they ignore the effects of system integration. In...

    Provided By European Design and Automation Association

  • White Papers // Feb 2010

    Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC - A Case Study

    In this paper, the authors examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. They present several design choices and focus on the power optimization of the NoC while achieving the required performance. They design steps include module mapping and allocation of...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    DRAM Selection and Configuration for Real-Time Mobile Systems

    The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both real-time and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    Memory-Map Selection for Firm Real-Time SDRAM Controllers

    A modern real-time embedded system must support multiple concurrently running applications. To reduce costs, critical SoC components like SDRAM memories are often shared between applications with a variety of firm real-time requirements. To guarantee that the system works as intended, the memory controller must be configured such that all the...

    Provided By European Design and Automation Association

  • White Papers // Dec 2011

    A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

    Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC implementations have been presented in the literature, some of them having mature tool-flows and ecosystems. The main differentiating factor between the various implementations are the services...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    Architectures and Modeling of Predictable Memory Controllers for Improved System Integration

    Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with real-time requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified together, resulting in...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, the authors suggest to partition a Network-on-Chip (NoC) based system into smaller sub-systems...

    Provided By European Design and Automation Association

  • White Papers // Dec 2010

    Optimal Scheduling of Switched FlexRay Networks

    This paper introduces the concept of switched FlexRay networks and proposes two algorithms to schedule data communication for this new type of network. Switched FlexRay networks use an intelligent star coupler, called a switch, to temporarily decouple network branches, thereby increasing the effective network bandwidth. Although scheduling for basic FlexRay...

    Provided By European Design and Automation Association

  • White Papers // Mar 2009

    Recursion-Driven Parallel Code Generation for Multi-Core Platforms

    The authors present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursive programming model is a good match for parallel systems because it highlights the temporal and spatial locality of data use. Recursive algorithms are used by Huckleberry's code generator not...

    Provided By European Design and Automation Association

  • White Papers // Mar 2012

    Compositional System-Level Design Exploration With Planning of High-Level Synthesis

    The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration the authors present three main contributions: a concise library format for characterization and reuse...

    Provided By European Design and Automation Association

  • White Papers // Dec 2012

    Sensor-Wise Methodology to Face NBTI Stress of NoC Buffers

    Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding

    In this paper, the authors present a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This Application-Specific Instruction-set Processor (ASIP) has SIMD architecture with a specialized and extensible instruction-set and 5-stages...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance

    Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially in arithmetic operations (where some bits are required later than others and some bits are produced earlier than others). This paper proposes a...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications

    In this paper, the authors present the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the Heterogeneous IP Block Interconnection (HIBI)...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC

    The authors' concept of Virtual Transaction Layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Vulnerability Analysis of L2 Cache Elements to Single Event Upsets

    Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the probability of particle strikes in these elements is high and can significantly impact overall processor reliability. Previous paper has developed effective metrics...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Automatic March Tests Generations for Static Linked Faults in SRAMs

    Memories are one of the most important components in digital systems, and semiconductor memories are now-a-days one of the fastest growing technologies. Actually the major trend of System-on-Chip (SoC) allows to embed in a single chip all the components and functions that historically were placed on a hardware board. Static...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Microarchitectural Floorplanning Under Performance and Thermal Tradeoff

    In this paper, the authors present the first multi-objective microarchitectural floorplanning algorithm for designing high-performance, high-reliability processors in the early design phase. Their floorplanner takes a microarchitectural netlist and determines the placement of the functional modules while simultaneously optimizing for performance and thermal reliability. The traditional design objectives such as...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Area-Efficient Error Protection for Caches

    Due to increasing concern about various errors, current processors adopt error protection mechanisms. Especially, protecting L2/L3 caches incur as much as 12.5% area overhead due to error correcting codes. Considering large L2/L3 caches of current processors, the area overhead is very high. This paper proposes an area-efficient error protection scheme...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Formal Verification of SystemC Designs Using a Petri-Net Based Representation

    Embedded electronic devices are often highly safety critical, such as in automotive and avionics applications or medical equipment. It is both very error-prone and time-consuming to design these complex systems. This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count

    The sensitivity of the response of an analog system to circuit parameter variations is a vital performance metric for evaluation of its quality. This paper proposes a unified high level synthesis methodology for higher order continuous time state variable filters, considering the optimization of this metric. Minimization of the hardware...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Space of DRAM Fault Models and Corresponding Testing

    DRAMs play an important role in the semi-conductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of fault models specifically designed to describe the faulty behavior of DRAMs. The fault models in this paper are the outcome of a...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Functional Test Generation using Property Decompositions for Validation of Pipelined Processors

    Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The...

    Provided By European Design and Automation Association

  • White Papers // Feb 2006

    Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors

    Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation Tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs is currently...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads

    Future computing clusters will prevalently run parallel workloads to take advantage of the increasing number of cores on chips. In tandem, there is a growing need to reduce energy consumption of computing. One promising method for improving energy efficiency is co-scheduling applications on compute nodes. Efficient consolidation for parallel workloads...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Power Management of Multi-Core Chips: Challenges and Pitfalls

    Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, the authors examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that they pose is: How to ensure that such managed systems are \"Energy-secure\" and how to pursue pre-silicon...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints

    In this paper, the authors consider distributed real-time embedded systems in which confidentiality of the internal communication is critical. They present an approach to efficiently implement cryptographic algorithms by using hardware/software co-design techniques. The objective is to find the minimal hardware overhead and corresponding process mapping for encryption and decryption...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems

    In this paper, the authors present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by Dynamic Voltage and Frequency Scaling (DVFS) methods in the presence of systematic and random variations. They show that maximum rejection for Process, Voltage and Temperature (PVT)...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Ultra Low Power Litho Friendly Local Assist Circuitry For Variability Resilient 8T SRAM

    Read-decoupled 8T SRAM cell offers a higher degree of variability resilience compared to 6T SRAM cell at the expense of an increased area overhead. This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Predicting Best Design Trade-offs: A Case Study in Processor Customization

    Given the high level description of a task, many different hardware modules may be generated while meeting its behavioral requirements. The characteristics of the generated hardware can be tailored to favor energy efficiency, performance and accuracy or die area. The inherent trade-offs between such metrics need to be explored in...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    SAFER PATH: Security Architecture using Fragmented Execution and Replication for Protection Against Trojaned Hardware

    Ensuring electronic components are free from Hardware Trojans is a very difficult task. Research suggests that even the best pre- and post-deployment detection mechanisms will not discover all malicious inclusions, nor prevent them from being activated. For economic reasons electronic components are used regardless of the possible presence of such...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions

    Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Refinement of UML/MARTE Models for the Design of Networked Embedded Systems

    Network design in distributed embedded applications is a novel challenging task which requires the extraction of communication requirements from application specification and the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/ MARTE as specification front-end and repository of refined versions...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller

    Modern System-on-Chip (SoC) designs are very complex and, thus, very hard to simulate and verify. The conventional Register Transfer Level (RTL) modeling is of too fine granularity to allow whole system designs to be rapidly simulated or used as virtual prototypes. Therefore, another more abstract level of modeling, namely Electronic...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    MAPG: Memory Access Power Gating

    In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this paper, the authors propose and model Memory Access Power Gating (MAPG), a...

    Provided By European Design and Automation Association

  • White Papers // Jan 2012

    Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis

    System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level...

    Provided By European Design and Automation Association

  • White Papers // Feb 2008

    Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography

    Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, the authors propose a low overhead...

    Provided By European Design and Automation Association