Hindawi Publishing

Displaying 361-400 of 1568 results

  • White Papers // Jan 2011

    List Decoding of Generalized Reed-Solomon Codes by Using a Modified Extended Key Equation Algorithm

    This paper presents a modified extended key equation algorithm in list decoding of Generalized Reed-Solomon (GRS) codes. A list decoding algorithm of generalized Reed-Solomon codes has two steps, interpolation and factorization. The Extended Key Equation algorithm (EKE) is an interpolation-based approach with a lower complexity than Sudan's algorithm. To increase...

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  • White Papers // Nov 2009

    Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

    The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal for dataflow applications with large amount of data. On the opposite, point-to-point communications are designed from the...

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  • White Papers // Oct 2009

    FPSoC-Based Architecture for a Fast Motion Estimation Algorithm in H.264/AVC

    There is an increasing need for high quality video on low power, portable devices. Possible target applications range from entertainment and personal communications to security and health care. While H.264/AVC answers the need for high quality video at lower bit rates, it is significantly more complex than previous coding standards...

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  • White Papers // Dec 2009

    Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding

    The authors present the design and VLSI implementation of a novel low-power bitstream-residual decoder for H.264/AVC baseline profile. It comprises a syntax parser, a parameter decoder, and an Inverse Quantization Inverse Transform (IQIT) decoder. The syntax parser detects and decodes each incoming codeword in the bitstream under the control of...

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  • White Papers // Nov 2009

    Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture

    This paper presents the design of an FPGA-based MultiProcessor-System-on-Chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive radar to track the speed and relative position of all the vehicles (targets) within its field of view. As the number of targets increases,...

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  • White Papers // Oct 2009

    Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

    Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models...

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  • White Papers // Oct 2009

    Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures

    This paper presents an efficient dynamic and run-time Hardware/Software scheduling approach. This scheduling heuristic consists in mapping online the different tasks of a highly dynamic application in such a way that the total execution time is minimized. The authors consider soft real-time data flow graph oriented applications for which the...

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  • White Papers // Sep 2009

    OLLAF: A Fine Grained Dynamically Reconfigurable Architecture for OS Support

    Fine Grained Dynamically Reconfigurable Architecture (FGDRA) offers a flexibility for embedded systems with a great power processing efficiency by exploiting optimizations opportunities at architectural level thanks to their fine configuration granularity. But this increase design complexity that should be abstracted by tools and operating system. In order to have a...

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  • White Papers // Sep 2009

    Very Low-Memory Wavelet Compression Architecture Using Strip-Based Processing for Implementation in Wireless Sensor Networks

    This paper presents a very low-memory wavelet compression architecture for implementation in severely constrained hardware environments such as Wireless Sensor Networks (WSNs). The approach employs a strip-based processing technique where an image is partitioned into strips and each strip is encoded separately. To further reduce the memory requirements, the wavelet...

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  • White Papers // Sep 2009

    An Open Framework for Rapid Prototyping of Signal Processing Applications

    Embedded real-time applications in communication systems have significant timing constraints, thus requiring multiple computation units. Manually exploring the potential parallelism of an application deployed on multicore architectures is greatly time-consuming. This paper presents an open-source Eclipse-based framework which aims to facilitate the exploration and development processes in this context. The...

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  • White Papers // Oct 2009

    A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning

    A mixed-signal embedded system called Intelligent Sensor InterFace (ISIF) suited to fast identify, trim, and verify an architecture to interface a given sensor is presented. This system has been developed according to a platform-based design approach, a methodology that has proved to be efficient for building complex mixed-signal embedded systems...

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  • White Papers // Feb 2010

    Design Methodologies and Innovative Architectures for Mixed-Signal Embedded Systems

    The continuous evolution of VLSI technologies, especially CMOS and its variants (HVMOS, BCD, RF CMOS, etc.), has enabled the integration of complex functionalities in a single, heterogeneous embedded system. Digital subsystems, such as microprocessors,memories, or communication interfaces, can be integrated onto the same substrate (System-on-Chip) or the same package (System-in-Package)...

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  • White Papers // Dec 2009

    On Mixed Abstraction

    Executable specifications and simulations are cornerstone to system design flows. Complex-mixed-signal embedded systems can be specified with SystemC AMS which supports abstraction and extensible models of computation. The language contains semantics for module connections and synchronization required in analog and digital interaction. Through the synchronization layer, user defined models of...

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  • White Papers // Feb 2010

    A Platform-Based Methodology for System-Level Mixed-Signal Design

    The complexity of today's embedded electronic systems as well as their demanding performance and reliability requirements are such that their design can no longer be tackled with ad hoc techniques while still meeting tight time to-market constraints. In this paper, the authors present a system level design approach for electronic...

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  • White Papers // Dec 2009

    Model and Design of a Power Driver for Piezoelectric Stack Actuators

    In linear piezoelectricity, the equations of linear elasticity are coupled to the charge equation of electrostatics by means of the piezoelectric constants. However, the electric variables are not purely static, but only quasistatic, because of the coupling to the dynamic mechanical equations. The aim is to obtain an analytical model...

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  • White Papers // Oct 2009

    A Systematic Development Methodology for Mixed-Mode Behavioral Models of In-Vehicle

    The rising demands for safety, power-weight reduction, and comfort make the in-vehicle network of embedded electronic systems very complex. In particular system reliability is essential, especially because of the safety requirements. Test and verification of the entire in-vehicle network by means of behavioral simulations are each time more widely adopted....

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  • White Papers // Jun 2010

    Design Criteria for Hierarchical Exclusive Code with Parameter-Invariant Decision Regions for Wireless 2-Way Relay Channel

    The unavoidable parametrization of the wireless link represents a major problem of the network-coded modulation synthesis in a 2-way relay channel. Composite (hierarchical) codeword received at the relay is generally parametrized by the channel gain, forcing any processing on the relay to be dependent on channel parameters. In this paper,...

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  • White Papers // Jan 2011

    Design and Implementation of a Lightweight Security Model to Prevent IEEE 802.11 Wireless DoS Attacks

    The protection offered by IEEE 802.11 security protocols such as WEP, WPA, and WPA2 does not govern wireless control frames. The control frames are transmitted in clear-text form, and there is no way to verify their validity by the recipients. The flaw of control frames can be exploited by attackers...

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  • White Papers // Apr 2010

    An Interference-Aware Admission Control Design for Wireless Mesh Networks

    In this paper, the authors present IAC, an interference aware admission control algorithm for use in wireless mesh networks. The core concept of IAC is to use a low overhead dual threshold based approach to share the bandwidth information with its neighbors in the interfering range. As a result, IAC...

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  • White Papers // Aug 2010

    Adaptive Resource Allocation with Strict Delay Constraints in OFDMA System

    Harsh wireless channel conditions, scarce bandwidth, and limited power resources require intelligent allocation schemes which can efficiently exploit channel variations. OFDMA is a multi-carrier modulation and multiplexing technique which divides the wide-band frequency selective wireless channel into a set of orthogonal narrow-band channels and provides immunity from Inter-Symbol Interference (ISI)....

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  • White Papers // Mar 2010

    Spectrum Sensing for Cognitive Radios with Transmission Statistics: Considering Linear Frequency Sweeping

    The spectrum sensing performance of Cognitive Radios (CRs) considering noisy signal measurements and the time domain transmission statistics of the Primary User (PU) is considered in this paper. When the spectrum is linearly swept in the frequency domain continuously to detect the presence of the PU the time-domain statistics of...

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  • White Papers // Mar 2010

    On the Capacity of FSO Links over Gamma-Gamma Atmospheric Turbulence Channels Using OOK Signaling

    A new upper bound on the capacity of power- and bandwidth-constrained optical wireless links over gamma-gamma atmospheric turbulence channels with intensity modulation and direct detection is derived when On-Off Keying (OOK) formats are used. In this Free-Space Optical (FSO) scenario, unlike previous capacity bounds derived from the classic capacity of...

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  • White Papers // Dec 2009

    Design of Orthogonal Filtered Multitone Modulation Systems and Comparison among Efficient Realizations

    The authors address the efficient realization of a Filtered Multi-Tone (FMT) modulation system and its orthogonal design. FMT modulation can be viewed as a Discrete Fourier Transform (DFT) modulated Filter Bank (FB). It generalizes the popular Orthogonal Frequency Division Multiplexing (OFDM) scheme by deploying frequency confined sub-channel pulses. They compare...

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  • White Papers // Jul 2010

    A Novel Real-Time Coal Miner Localization and Tracking System Based on Self-Organized Sensor Networks

    With the development of information technology, the authors envision that the key of improving coal mine safety is how to get real-time positions of miners. In this paper, they propose a prototype system for real-time coal miner localization and tracking based on self-organized sensor networks. The system is composed of...

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  • White Papers // Aug 2010

    Suboptimal Partial Transmit Sequence-Active Interference Cancellation with Particle Swarm Optimization

    Active Interference Cancellation (AIC) is an effective technique to provide interference avoidance feature for an Ultra-WideBand (UWB) OFDM transmitter. Partial Transmit Sequence-AIC (PTS-AIC), which was recently proposed as an improvement of AIC, requires high computational complexity by doing the exhaustive search of all possible weighting factors whose number grows exponentially...

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  • White Papers // Feb 2010

    A Next Generation Wireless Simulator Based on MIMO-OFDM: LTE Case Study

    The complexity of next generation wireless systems is growing exponentially. The combination of Multiple-Input-Multiple-Output (MIMO) technology with Orthogonal Frequency Division Multiplexing (OFDM) is considered as the best solution to provide high data rates under frequency-selective fading channels. The design and evaluation of MIMO-OFDM systems require a detailed analysis of a...

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  • White Papers // Nov 2010

    Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

    This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The...

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  • White Papers // Nov 2010

    FPGA Implementation for GMM-Based Speaker Identification

    In today's society, highly accurate personal identification systems are required. Passwords or pin numbers can be forgotten or forged and are no longer considered to offer a high level of security. The use of biological features, biometrics, is becoming widely accepted as the next level for security systems. Biometric-based speaker...

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  • White Papers // Nov 2010

    An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms

    The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an architecture that meets performance and power consumption requirements. Thus, developing new high-level specification mechanisms for the reduction...

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  • White Papers // Oct 2010

    A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

    This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840?2048) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve...

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  • White Papers // Sep 2010

    A Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture

    Mathematical morphology supplies powerful tools for low-level image analysis. Many applications in computer vision require dedicated hardware for real-time execution. The design of morphological operators for a given application is not a trivial one. Genetic programming is a branch of evolutionary computing, and it is consolidating as a promising method...

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  • White Papers // Sep 2010

    FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

    A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST) to compile sentence, word, and phoneme models. The system comprises a software back-end search and an FPGA-based Gaussian calculation which are covered here....

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  • White Papers // Dec 2010

    A Reconfigurable System Approach to the Direct Kinematics of a 5 D.o.f Robotic Manipulator

    Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 Degrees of Freedom (5...

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  • White Papers // Dec 2010

    Low-Complexity Online Synthesis for AMIDAR Processors

    Future chip technologies will change the way the authors deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been...

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  • White Papers // Dec 2010

    Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

    Field-Programmable Gate Arrays (FPGAs) and other Reconfigurable Computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of...

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  • White Papers // Dec 2010

    Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

    Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at run-time provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, the authors...

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  • White Papers // Oct 2010

    Robotic Mapping and Localization with Real-Time Dense Stereo on Reconfigurable Hardware

    A reconfigurable architecture for dense stereo is presented as an observation framework for a real-time implementation of the simultaneous localization and mapping problem in robotics. The reconfigurable sensor detects point features from stereo image pairs to use at the measurement update stage of the procedure. The main hardware blocks are...

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  • White Papers // Nov 2010

    RapidRadio: A Domain-Specific Productivity? Enhancing Framework

    The RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity enhancing tool that reduces the required knowledge-base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of...

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  • White Papers // Oct 2010

    Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm

    Multivariate polynomial interpolation is a key computation in many areas of science and engineering and, in the authors' case, is crucial for the solution of the reverse engineering of genetic networks modeled by finite fields. Faster implementations of such algorithms are needed to cope with the increasing quantity and complexity...

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  • White Papers // Oct 2010

    Reconfigurable Multiprocessor Systems: A Review

    Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uni-processor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware....

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