Hindawi Publishing

Displaying 1681-1698 of 1698 results

  • White Papers // Apr 2009

    An FPGA Implementation of a Parallelized MT19937 Uniform Random Number Generator

    Recent times have witnessed an increase in use of high-performance reconfigurable computing for accelerating large-scale simulations. A characteristic of such simulations, like InfraRed (IR) scene simulation, is the use of large quantities of uncorrelated random numbers. It is therefore of interest to have a fast uniform random number generator implemented...

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  • White Papers // Mar 2009

    APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    The authors present a software environment for the efficient simulation of Cellular Processor Arrays (CPAs). This software APRON (Array Processing enviRONment) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software...

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  • White Papers // Feb 2009

    Flat Array Antennas for Ku-Band Mobile Satellite Terminals

    This paper presents the advances in the development of two innovative flat array antennas for Ku-band mobile satellite terminals. The first antenna is specifically conceived for double-deck trains to allow a bi-directional high data rate satellite link. The available circular surface (diameter 80 cm) integrates both a transmitting and a...

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  • White Papers // Jan 2009

    Autocorrelation Properties of OFDM Timing Synchronization Waveforms Employing Pilot Subcarriers

    The authors investigate the autocorrelation properties of timing synchronization waveforms that are generated by embedded frequency domain pilot tones in Orthogonal Frequency Division Multiplex (OFDM) systems. The waveforms are composed by summing a selected number of OFDM subcarriers such that the AutoCorrelation Function (ACF) of the resulting time waveform has...

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  • White Papers // Dec 2008

    Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing

    High-Performance Reconfigurable Computing (HPRC) is a novel approach to provide large-scale computing power to modern scientific applications. Using both General-Purpose Processors (GPPs) and FPGAs allows application designers to exploit fine-grained and coarse-grained parallelism, achieving high degrees of speedup. One scientific application that benefits from this technique is backprojection, an image...

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  • White Papers // Nov 2008

    Influence of the Cavitation Model on the Simulation of Cloud Cavitation on 2D Foil Section

    For numerical simulations of cavitating flows, many physical models are currently used. One approach is the void fraction transport equation-based model including source terms for vaporization and condensation processes. Various source terms have been proposed by different researchers. However, they have been tested only in different flow configurations, which make...

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  • White Papers // Sep 2008

    A Programmable Max-Log-MAP Turbo Decoder Implementation

    Telecommunications devices conforming with 3G standards are targeted on high volume consumer markets. For this reason, there is a real need for highly optimized structures where every advantage is taken to achieve cost efficiency. In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems,...

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  • White Papers // Sep 2008

    Discrete-Time Second-Order Distributed Consensus Time Synchronization Algorithm for Wireless Sensor Networks

    This paper proposes a novel discrete-time Second-Order Distributed Consensus Time Synchronization (SO-DCTS) algorithm for wireless sensor networks. The consensus properties and convergence rates of the SO-DCTS algorithm are analyzed for both directed and undirected networks. Additionally, the convergence region and optimal convergence rate of the SO-DCTS algorithm are determined for...

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  • White Papers // Apr 2008

    Detection of Variations of Local Irregularity of Traffic Under DDOS Flood Attack

    The aim of Distributed Denial-of-Service (DDOS) flood attacks is to overwhelm the attacked site or to make its service performance deterioration considerably by sending flood packets to the target from the machines distributed all over the world. This is a kind of local behavior of traffic at the protected site...

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  • White Papers // Feb 2008

    On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

    The authors investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits; however, these previous studies did not evaluate the impact on power. In this paper, they measure...

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  • White Papers // Jan 2008

    Embedded Systems Design in Intelligent Industrial Automation

    Industrial Automation (IA) is the vast area of embedded computing devoted to industrial applications. Apart from many tailored solutions (numerical controllers, hardware controllers, etc.) the scene is dominated by programmable logic controllers, widely known by the abbreviation PLC, which represent the most wide-spread class of embedded computing platforms. In the...

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  • White Papers // Nov 2007

    Industrial TCP/IP Services Monitoring Through Embedded Web Services

    The amount of IT devices and services incorporated in the industrial environment has led to the need to design mechanisms that will ensure its correct operation and minimize stoppage times. This paper proposes a system based on service-oriented architectures that allow the correct operation and monitoring of the applications and...

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  • White Papers // Jun 2007

    A Framework for System-Level Modeling and Simulation of Embedded Systems Architectures

    The high complexity of modern embedded systems impels designers of such systems to model and simulate system components and their interactions in the early design stages. It is therefore essential to develop good tools for exploring a wide range of design choices at these early stages, where the design space...

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  • White Papers // May 2007

    On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration

    In this paper, the authors present the necessary steps to modify the implementation of the SPARCV8 architecture to enhance it with multimedia oriented instructions. The purpose is improving video compression performance without designing dedicated coprocessors. They investigate the complexity of modifying a standard processor instruction set and show that, although...

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  • White Papers // Mar 2007

    A Shared Memory Module for Asynchronous Arrays of Processors

    A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and...

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  • White Papers // Dec 2006

    Real-Time Video Convolutional Face Finder on Embedded Platforms

    A high-level optimization methodology is applied for implementing the well-known Convolutional Face Finder (CFF) algorithm for real-time applications on mobile phones, such as teleconferencing, advanced user interfaces, image indexing, and security access control. CFF is based on a feature extraction and classification technique which consists of a pipeline of convolutions...

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  • White Papers // Oct 2006

    Embedded Vehicle Speed Estimation System Using an Asynchronous Temporal Contrast Vision Sensor

    In this paper, the authors present an embedded multilane traffic data acquisition system based on an asynchronous temporal contrast vision sensor, and algorithms for vehicle speed estimation developed to make efficient use of the asynchronous high-precision timing information delivered by this sensor. The vision sensor features high temporal resolution with...

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  • White Papers // Jul 2006

    Customizing Multiprocessor Implementation of an Automated Video Surveillance System

    Recent advances of computer technology have made real-time automated video surveillance possible. Automated video surveillance can monitor large areas with complex scenes and can be employed to increase the probability of specific incident detection and at the same time can reduce the volume of data presented to security personnel. This...

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