Hindawi Publishing

Displaying 201-240 of 1748 results

  • White Papers // Jul 2011

    Exploring Many-Core Design Templates for FPGAs and ASICs

    The authors present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or...

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  • White Papers // Sep 2011

    Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

    A Hybrid router architecture for Networks-on-Chip "NoC" is presented, it combines Spatial Division Multiplexing "SDM" based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing "TDM" technique in...

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  • White Papers // Sep 2011

    A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

    This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for Software Defined Radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features....

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  • White Papers // Jul 2011

    PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

    Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, the authors propose PCIU, a novel classification...

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  • White Papers // Apr 2009

    In-Network Adaptation of Video Streams Using Network Processors

    The increasing variety of networks and end systems, especially wireless devices, pose new challenges in communication support for, particularly,multicast-based collaborative applications. In traditional multicasting, the sender transmits video at the same rate and resolution to all receivers independent of their network characteristics, end system equipment, and users' preferences about video...

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  • White Papers // Nov 2008

    Remote Laboratory Experiments in a Virtual Immersive Learning Environment

    The Virtual Immersive Learning (VIL) test bench implements a virtual collaborative immersive environment, capable of integrating natural contexts and typical gestures, which may occur during traditional lectures, enhanced with advanced experimental sessions. The system architecture is described, along with the motivations, and the most significant choices, both hardware and software,...

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  • White Papers // Sep 2008

    Enabling Cognitive Load-Aware AR with Rateless Coding on a Wearable Network

    Augmented Reality (AR) on a head-mounted display is conveniently supported by a wearable wireless network. If, in addition, the AR display is moderated to take account of the cognitive load of the wearer, then additional biosensors form part of the network. In this paper, the impact of these additional traffic...

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  • White Papers // Aug 2008

    Traffic and Quality Characterization of the H.264/AVC Scalable Video Coding Extension

    The recent Scalable Video Coding (SVC) extension to the H.264/AVC video coding standard has unprecedented compression efficiency while supporting a wide range of scalability modes, including temporal, patial, and quality (SNR) scalability, as well as combined spatiotemporal SNR scalability. The traffic characteristics, especially the bit rate variabilities, of the individual...

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  • White Papers // Feb 2011

    A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices

    Public Key Cryptography enables entity authentication protocols based on a platform's knowledge of other platforms' public key. This is particularly advantageous for embedded systems, such as FPGA platforms, with limited or none read-protected memory resources. For access control systems, an access token is authenticated by the mobile system. Only the...

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  • White Papers // Feb 2011

    Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

    The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and run-time to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design...

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  • White Papers // Dec 2010

    Experiment Centric Teaching for Reconfigurable Processors

    This paper presents a setup for teaching configware to master students. The authors' approach focuses on experiment and leaning-by-doing while being supported by research activity. The central project they submit to students addresses building up a simple RISC processor, that supports an extensible instructions set thanks to its reconfigurable functional...

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  • White Papers // Jul 2011

    Reduced-Precision Redundancy on FPGAs

    Reduced-Precision Redundancy (RPR) has been shown to be a viable alternative to Triple Modular Redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve reliability in soft error environments. Example implementations and fault injection experiments...

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  • White Papers // May 2011

    AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

    With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration....

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  • White Papers // Jun 2011

    Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

    As reconfigurable devices' capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. Organic computing paradigms have been proposed for fault-tolerant systems because they promote behaviors that allow complex digital systems to adapt and survive in demanding environments. In this...

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  • White Papers // Jun 2011

    A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

    Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of Dynamic Partial Reconfiguration (DPR) controllers has been limited by its use of the Processor...

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  • White Papers // Apr 2011

    Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

    This special issue of IJRC includes papers selected from the 17th Reconfigurable Architectures Workshop (RAW 2010) held in Atlanta, GA, USA, in April 29-30, 2010. RAW 2010 was associated with the 24th Annual International Parallel & Distributed Processing Symposium (IPDPS 2010) and was sponsored by the IEEE Computer Society Technical...

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  • White Papers // Mar 2011

    A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

    The authors introduce a specialized self-checking hardware journal being used as a centerpiece in their design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous...

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  • White Papers // Feb 2011

    Exploring Online Synthesis for CGRAs with Specialized Operator Sets

    The design of energy-efficient systems has become a major challenge for engineers over the last decade. One way to save energy is to spread out computations in space rather than in time (as traditional processors do). Unfortunately, this requires to design specialized hardware for each application. Also, the nonrecurring expenses...

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  • White Papers // Mar 2011

    A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

    Kahn Process Networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this paper, the authors propose a task-aware middleware concept...

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  • White Papers // Feb 2011

    Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

    Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these...

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  • White Papers // Feb 2011

    FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

    Reconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics. A key challenge for achieving high performance with reconfigurable accelerators is the efficient utilization of the available memory resources. A detailed knowledge of the...

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  • White Papers // Jun 2011

    Real-Time Adaptive Content-Based Synchronization of Multimedia Streams

    Traditional synchronization schemes of multimedia applications are based on temporal relationships between inter- and intrastreams. These schemes do not provide good synchronization in the presence of random delay. As a solution, this paper proposes an adaptive content-based synchronization scheme that synchronizes multimedia streams by accounting for content in addition to...

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  • White Papers // Apr 2011

    A Reliable Event-Driven Strategy for Real-Time Multiple Object Tracking Using Static Cameras

    Recently, because of its importance in computer vision and surveillance systems, object tracking has progressed rapidly over the last two decades. Researches on such systems still face several theoretical and technical problems that badly impact not only the accuracy of position measurements but also the continuity of tracking. In this...

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  • White Papers // Mar 2011

    Fast Retrieval Algorithm for Earth Mover's Distance Using EMD Lower Bounds and a Skipping Algorithm

    The Earth Mover's Distance (EMD) is a measure of the distance between two distributions, and it has been widely used in multimedia information retrieval systems, in particular, in content-based image retrieval systems. When the EMD is applied to image problems based on color or texture, the EMD reflects the human...

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  • White Papers // Jan 2011

    From Community Detection to Mentor Selection in? Rating-Free Collaborative Filtering

    The number of items that users can now access when navigating on the Web is so huge that these might feel lost. Recommender systems are a way to cope with this profusion of data by suggesting items that fit the users needs. One of the most popular techniques for recommender...

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  • White Papers // Jul 2010

    Open Profiling of Quality: A Mixed Method Approach to Understanding Multimodal Quality Perception

    To quantify the excellence of multimedia quality, subjective evaluation experiments are conducted. In these experiments, the tradition of quantitative assessment is the most dominating, but it disregards the understanding of participants' interpretations, descriptions, and the evaluation criteria of quality. The goal of this paper is to present a new multimedia...

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  • White Papers // Jul 2010

    MMSA: Metamodel Multimedia Software Architecture

    Interoperability explains how two or more systems or components exchange and process information. The heterogeneity communication mechanisms of the components (GPRS, WIFI, Bluetooth, ZigBee, etc.), transmission speed, as well as the variety of the media (sound, video, text, and image) they manage have a strong influence on the interoperability. That...

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  • White Papers // Jun 2010

    UEP Concepts in Modulation and Coding

    First Unequal Error Protection (UEP) proposals date back to the 1960's (Masnick and Wolf; 1967), but now with the introduction of scalable video, UEP develops to a key concept for the transport of multimedia data. The paper presents an overview of some new approaches realizing UEP properties in physical transport,...

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  • White Papers // Jul 2009

    Sketch-Based Spatial Queries for the Retrieval of Human Locomotion Patterns in Smart Environments

    A system for retrieving video sequences created by tracking humans in a smart environment, by using spatial queries, is presented. Sketches made with a pointing device on the floor layout of the environment are used to form queries corresponding to locomotion patterns. The sketches are analyzed to identify the type...

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  • White Papers // Jun 2009

    Adaptive Packet-Level Interleaved FEC for Wireless? Priority-Encoded Video Streaming

    Packet-level Forward Error Control (FEC) for video streaming over a wireless network has received comparatively limited investigation, because of the delay introduced by the need to assemble a group of packets. However, packet-level interleaving when combined with FEC presents a remedy to time-correlated error bursts, though it can further increase...

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  • White Papers // May 2009

    A Survey of Visual Sensor Networks

    Visual sensor networks have emerged as an important class of sensor-based distributed intelligent systems, with unique performance, complexity, and quality of service challenges. Consisting of a large number of low-power camera nodes, visual sensor networks support a great number of novel vision-based applications. The camera nodes provide information from a...

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  • White Papers // Jan 2011

    A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

    In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several arithmetic cores for parallel processing while supporting...

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  • White Papers // Jan 2011

    A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm

    The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. The authors present the design of an efficient, pipelined floating-point datapath for calculating the logarithm function on reconfigurable devices. They integrate the datapath into a stand-alone LUT-based (Lookup...

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  • White Papers // Jan 2011

    On Self-Timed Circuits in Real-Time Systems

    While asynchronous logic has many potential advantages compared to traditional synchronous designs, one of the major drawbacks is its unpredictability with respect to temporal behavior. Having no high-precision oscillator, a self-timed circuit's execution speed is heavily dependent on temperature and supply voltage. Small fluctuations of these parameters already result in...

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  • White Papers // Jan 2011

    An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation

    This paper describes the development of a fast adaptable FPGA-based wide-band channel sounder with signal bandwidths of up to 200MHz and channel sampling rates up to 5.4 kHz. The application of FPGA allows the user to vary the number of real-time channel response averages, channel sampling interval, and duration of...

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  • White Papers // Dec 2010

    The Potential for a GPU-Like Overlay Architecture for FPGAs

    The authors propose a soft processor programming model and architecture inspired by Graphics Processing Units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, their soft processor architecture exploits multi-threading, vector operations, and predication to supply a floating-point pipeline of 64 stages...

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  • White Papers // Dec 2010

    An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads

    Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating along graph edges. The authors can statically expose this structure to traffic compilers and optimization tools to reshape and reduce traffic for higher performance (or lower area, lower energy,...

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  • White Papers // Jan 2011

    A Streaming High-Throughput Linear Sorter System with Contention Buffering

    Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their...

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  • White Papers // Dec 2010

    Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates

    The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can increase application's speed through TLP exploitation, this speedup is still limited to the amount of parallelism available in the application, as demonstrated...

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  • White Papers // Dec 2010

    Floorplacement for Partial Reconfigurable FPGA-Based Systems

    The authors presented a resource- and configuration-aware floor-placement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Their work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based...

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