Hiroshima University

Displaying 1-11 of 11 results

  • White Papers // Jan 2014

    Implementations of the Hough Transform on the Embedded Multicore Processors

    Embedded multicore processors represented by FPGAs and GPUs have lately attracted considerable attention for their potential computation ability and power consumption. Recent, FPGAs have hundreds of embedded DSP slices and block RAMs. For example, Xilinx Virtex-6 Family FPGAs have a DSP48E1 slice, which is a configurable logic block equipped with...

    Provided By Hiroshima University

  • White Papers // Apr 2013

    Quantitative Security Evaluation for Software System from Vulnerability Database

    Many security incidents have been reported in enterprise systems and personal computers, such as the denial-of-service attack via computer viruses and the data leak caused by unauthorized accesses. This paper proposes a quantitative security evaluation for software system from the vulnerability data consisting of discovery date, solution date and exploit...

    Provided By Hiroshima University

  • White Papers // Jan 2013

    Very Large-Scale Integrated Processor

    In the near future, improvements in semiconductor technology will allow thousands of resources to be implementable on chip. However, a limitation remains for both single large-scale processors and many-core processors. For single processors, this limitation arises from their design complexity, and regarding the many-core processors, an application is partitioned to...

    Provided By Hiroshima University

  • White Papers // Oct 2012

    Preamble Design for Joint Estimation of Channel and I/Q Imbalance in MIMO-OFDM Systems

    In this paper, preamble design for estimation of frequency selective channels and In-phase/Quadrature-phase (I/Q) imbalance in Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) systems is proposed. First the authors utilize convex optimization to optimize power of all active subcarriers, then they employ Cross Entropy (CE) optimization techniques to...

    Provided By Hiroshima University

  • White Papers // Jul 2012

    High-Performance Symmetric Block Ciphers on Multicore CPU and GPUs

    As the data protection with encryption becomes important day-by-day, the encryption processing using General Purpose computation on a Graphic Processing Unit (GPGPU) has been noticed as one of the methods to realize high-speed data protection technology. GPUs have evolved in recent years into powerful parallel computing devices, with a high...

    Provided By Hiroshima University

  • White Papers // Mar 2012

    Variants of Mersenne Twister Suitable for Graphic Processors

    A Graphic Processing Unit (GPU) is a highly parallel processor designed for computer graphics. GPUs are now widely used in both personal computers and game machines, and are cheap despite their high computational power. This paper proposes a type of pseudorandom number generator, Mersenne Twister for Graphic Processor (MTGP), for...

    Provided By Hiroshima University

  • White Papers // Jul 2011

    A Fine-Grained Algorithm for Non-Parametric Software Reliability Estimation

    In this paper, the authors improve a non-parametric order statistics-based software reliability model by Barghout, Littlewood and Abdel-Ghaly (1998), from the standpoints of estimation algorithm and reliability measure. More specifically, they introduce the kernel density estimation method with a truncated Gaussian kernel function and estimate the software fault-detection time distribution...

    Provided By Hiroshima University

  • White Papers // Jan 2011

    CHPS: An Environment for Collaborative Execution on Heterogeneous Desktop Systems

    Modern commodity desktop computers equipped with multi-core Central Processing Units (CPUs) and specialized but programmable co-processors are capable of providing a remarkable computational performance. However, approaching this performance is not a trivial task as it requires the coordination of architecturally different devices for cooperative execution. Coordinating the use of the...

    Provided By Hiroshima University

  • White Papers // Nov 2010

    Domain Decomposition Method on GPU Cluster

    Pallalel GPGPU computing for lattice QCD simulations has a bottleneck on the GPU to GPU data communication due to the lack of the direct data exchanging facility. In this work the authors investigate the performance of quark solver using the Restricted Additive Schwarz (RAS) preconditioner on a low cost GPU...

    Provided By Hiroshima University

  • White Papers // Jul 2010

    Estimating the Error Rate in an Apache Web Server System

    In this paper, the authors focus on the relationship between the error rate which is one of the representative reliability measures in Apache web servers and the system parameters which reflect on the web server's system performance, and develop a probability model to describe it. More specifically, they implement a...

    Provided By Hiroshima University

  • White Papers // Oct 2008

    PKI Based Semi-Fragile Watermark for Visual Content Authentication

    Multimedia content owners always endure of copyright protection and ownership verification of their digital assets. Robust watermarking techniques are invented to defeat these problems. However evolution of the watermarks focused different security aspects of multimedia data such as content integrity, data authentication, etc. As a result, fragile watermarking was introduced...

    Provided By Hiroshima University

  • White Papers // Jul 2012

    High-Performance Symmetric Block Ciphers on Multicore CPU and GPUs

    As the data protection with encryption becomes important day-by-day, the encryption processing using General Purpose computation on a Graphic Processing Unit (GPGPU) has been noticed as one of the methods to realize high-speed data protection technology. GPUs have evolved in recent years into powerful parallel computing devices, with a high...

    Provided By Hiroshima University

  • White Papers // Jan 2014

    Implementations of the Hough Transform on the Embedded Multicore Processors

    Embedded multicore processors represented by FPGAs and GPUs have lately attracted considerable attention for their potential computation ability and power consumption. Recent, FPGAs have hundreds of embedded DSP slices and block RAMs. For example, Xilinx Virtex-6 Family FPGAs have a DSP48E1 slice, which is a configurable logic block equipped with...

    Provided By Hiroshima University

  • White Papers // Jan 2011

    CHPS: An Environment for Collaborative Execution on Heterogeneous Desktop Systems

    Modern commodity desktop computers equipped with multi-core Central Processing Units (CPUs) and specialized but programmable co-processors are capable of providing a remarkable computational performance. However, approaching this performance is not a trivial task as it requires the coordination of architecturally different devices for cooperative execution. Coordinating the use of the...

    Provided By Hiroshima University

  • White Papers // Jan 2013

    Very Large-Scale Integrated Processor

    In the near future, improvements in semiconductor technology will allow thousands of resources to be implementable on chip. However, a limitation remains for both single large-scale processors and many-core processors. For single processors, this limitation arises from their design complexity, and regarding the many-core processors, an application is partitioned to...

    Provided By Hiroshima University

  • White Papers // Oct 2008

    PKI Based Semi-Fragile Watermark for Visual Content Authentication

    Multimedia content owners always endure of copyright protection and ownership verification of their digital assets. Robust watermarking techniques are invented to defeat these problems. However evolution of the watermarks focused different security aspects of multimedia data such as content integrity, data authentication, etc. As a result, fragile watermarking was introduced...

    Provided By Hiroshima University

  • White Papers // Nov 2010

    Domain Decomposition Method on GPU Cluster

    Pallalel GPGPU computing for lattice QCD simulations has a bottleneck on the GPU to GPU data communication due to the lack of the direct data exchanging facility. In this work the authors investigate the performance of quark solver using the Restricted Additive Schwarz (RAS) preconditioner on a low cost GPU...

    Provided By Hiroshima University

  • White Papers // Jul 2010

    Estimating the Error Rate in an Apache Web Server System

    In this paper, the authors focus on the relationship between the error rate which is one of the representative reliability measures in Apache web servers and the system parameters which reflect on the web server's system performance, and develop a probability model to describe it. More specifically, they implement a...

    Provided By Hiroshima University

  • White Papers // Jul 2011

    A Fine-Grained Algorithm for Non-Parametric Software Reliability Estimation

    In this paper, the authors improve a non-parametric order statistics-based software reliability model by Barghout, Littlewood and Abdel-Ghaly (1998), from the standpoints of estimation algorithm and reliability measure. More specifically, they introduce the kernel density estimation method with a truncated Gaussian kernel function and estimate the software fault-detection time distribution...

    Provided By Hiroshima University

  • White Papers // Oct 2012

    Preamble Design for Joint Estimation of Channel and I/Q Imbalance in MIMO-OFDM Systems

    In this paper, preamble design for estimation of frequency selective channels and In-phase/Quadrature-phase (I/Q) imbalance in Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) systems is proposed. First the authors utilize convex optimization to optimize power of all active subcarriers, then they employ Cross Entropy (CE) optimization techniques to...

    Provided By Hiroshima University

  • White Papers // Apr 2013

    Quantitative Security Evaluation for Software System from Vulnerability Database

    Many security incidents have been reported in enterprise systems and personal computers, such as the denial-of-service attack via computer viruses and the data leak caused by unauthorized accesses. This paper proposes a quantitative security evaluation for software system from the vulnerability data consisting of discovery date, solution date and exploit...

    Provided By Hiroshima University

  • White Papers // Mar 2012

    Variants of Mersenne Twister Suitable for Graphic Processors

    A Graphic Processing Unit (GPU) is a highly parallel processor designed for computer graphics. GPUs are now widely used in both personal computers and game machines, and are cheap despite their high computational power. This paper proposes a type of pseudorandom number generator, Mersenne Twister for Graphic Processor (MTGP), for...

    Provided By Hiroshima University