Indian Institute of Technology Kanpur

Displaying 1-40 of 63 results

  • White Papers // Jan 2014

    LEMap: Controlling Leakage in Large Chip-Multiprocessor Caches Via Prole-Guided Virtual Address Translation

    The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last level cache. However, larger caches threaten to dramatically increase the leakage power as the industry moves into deeper sub-micron technology. In...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2006

    PickPacket: A Distributed Parallel Architecture

    Use of computers and networks in information exchange has increased in the last few decades and led to establishment of high speed networks (up to 10 Gbps). These network speeds are approaching the memory interface speeds of general purpose processors. Monitoring networks with such high speed is not possible with...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2014

    Privacy Preserving Clustering using Fully Homomorphic Encryption

    In this paper, the authors focus on the privacy preserving scheme for distributed k-means clustering. Various techniques have been suggested in the literature for privacy preserving distributed clustering which is either cryptography based or non-cryptography based. In the non-cryptography based techniques, there is a trade-off between privacy and accuracy. Whereas...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Mar 2007

    Multilayer Semantic Data Model for Sports Video

    Content-based video management system has become an active research topic for many researchers, which can fully abstract the content of video and index the video objects. A hierarchical semantic abstraction for sports video is proposed in the paper. The authors have represented the semantics of sports video at three levels...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2014

    PageNUCA: Selected Policies for Page-Grain Locality Management in Large Shared Chip-Multiprocessor Caches

    As the last-level on-chip caches in Chip Multi-Processors (CMPs) increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform access latency seen by a core to different independent banks of a large cache spread over the chip necessitates active mechanisms for improving data...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2014

    Scavenger: A New Last Level Cache Architecture with Global Block Priority

    Addresses suffering from cache miss typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, the authors observe that the number of intervening misses at the last-level cache between the eviction of a particular block and its reuse can be very large, preventing traditional victim...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Sep 2012

    Performance Evaluation of Concurrent Lock-Free Data Structures on GPUs

    Graphics Processing Units (GPUs) have emerged as a strong candidate for high-performance computing. While regular data-parallel computations with little or no synchronization are easy to map on the GPU architectures, it is a challenge to scale up computations on dynamically changing pointer-linked data structures. The traditional lock-based implementations are known...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Sep 2008

    A Compilation Framework for Irregular Memory Accesses on the Cell Broadband Engine

    A class of scientific problems represents a physical system in the form of sparse and irregular kernels. Parallelizing scientific applications that comprise of sparse data structures on the Cell Broadband Engine (Cell BE) is a challenging problem as the memory access pattern is irregular and cannot be determined at compile...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2008

    Implementing a Parallel Matrix Factorization Library on the Cell Broadband Engine

    Matrix factorization (or often called decomposition) is a frequently used kernel in a large number of applications ranging from linear solvers to data clustering and machine learning. The central contribution of this paper is a thorough performance study of four popular matrix factorization techniques, namely, LU, Cholesky, QR, and SVD...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors

    Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate the user to explore memory compression potential in Distributed shared Memory (DSM) multiprocessors. This paper for the first time integrates on-the-fly cache block compression/decompression algorithms in the cache coherence protocols by leveraging the directory structure...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Feb 2007

    Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads

    Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication behavior on shared memory multiprocessors. However, these systems require custom hardware in the memory controller for cache line assembly/disassembly, address translation between re-mapped and normal addresses, and...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Nov 2008

    Cooling the Hot Sets: Improved Space Utilization in Large Caches via Dynamic Set Balancing

    Multi-megabyte on-chip last-level caches are commonplace in high-end computing platforms. Even though these caches are often designed to have very high associativity, they suffer from non-uniform utilization of the sets leading to a high volume of conflict misses. Clustering of physical addresses to a few hot sets happens partly due...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    Retargetable Cache Simulation Using High Level Processor Models

    During the design of modern embedded systems, it is necessary to automatically generate processor and application development tools like assemblers, disassemblers, compilers, instruction simulators etc. During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator....

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    High Level Synthesis from Sim-nML Processor Models

    The design of modern complex embedded systems requires a high level of abstraction of the design. The Sim-nML is a specification language to model processors for such designs. Several software generation tools have been developed that take ISA specifications in Sim-nML as input. In this paper, the authors present a...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    Processor Modeling for Hardware Software Codesign

    In hardware - software co-design paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific embedded systems necessitates high level system design tools for rapid prototyping. This paper involves design of a language Sim-nML which will be the base...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    Retargetable Program Profiling Using High Level Processor Models

    During the design of embedded systems, need is felt to automatically generate processor and application development tools like assemblers, disassemblers, compilers, instruction-set simulators etc. Automated generation of such tools yields faster turnaround time with lower costs for system design and simplifies the process of incorporating design changes. Program profiling helps...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // May 2007

    Processor Models for Retargetable Tools

    In applications that involve the development of application specific processors, often there is a need to generate various processor specific tools such as assemblers, compilers, simulators etc. In this paper, the authors describe a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators and compilers etc., using...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2014

    Some Experiments with the Performance of LAMP Architecture

    Measurements are very useful to gauge the actual performance of various architectures and their components. In this paper, the authors investigate the performance of the LAMP (Linux, Apache, MySQL, and PHP) architecture and MySQL and PHP components. They build a web-site using LAMP and measure the application level performance. They...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2014

    Comparative Analysis of Elliptic Curve Cryptography Based Algorithms to Implement Privacy Preserving Clustering Through Secure Multiparty Computation

    In this paper, the authors focus on elliptic curve cryptography based approach for Secure Multiparty Computation (SMC). Widespread proliferation of data and the growth of communication technologies have enabled collaborative computations among parties in distributed scenario. Preserving privacy of data owned by parties is crucial in such scenarios. Classical approach...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Aug 2006

    Network Monitoring Tool to Identify Malware Infected Computers

    These days most of the Organizational Networks are facing a critical problem. Lately there has been a lot of increase in Malwares such as worms, adwares, spywares etc., which get installed on the user's PC and generate Network and Internet traffic without the user's knowledge i.e. in the background. As...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jul 2009

    Accessing Files From Public Computers in a Trusted Manner

    Governments, military, different private organizations, financial institutions and hospitals have great deal of confidential information which is stored on computers. All these organizations want this information to be secure and accessible from any part of the world. For data security, one can use any of the encrypting file systems like...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2010

    Surveillance Video Mining

    This paper approaches the problem of surveillance event characterization at two levels. First, the information characterizable at the single camera image-plane level, where one uses a set of occlusion primitives to define a set of time-varying predicates on heterogeneous objects moving in unknown environments. After learning the scene background online,...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2011

    Rural Telephony: A Socio-Economic Case Study

    Information and Communication Technology (ICT) has the potential to bring in development to rural areas in the third world. Any deployment of technology however should be backed by a positive economic activity to be sustainable. This paper reports on experience with the economics, as well as the social aspects of...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jul 2009

    TransCrypt: An Enterprise Encrypting File System Over NFS

    Many organizations have great deal of confidential information which is stored on computers. Such information is desired to be kept securely yet giving a convenience of accessibility from any part of the world. For data security, one can use an encrypting file system such as eCryptfs, dmCrypt, File Vault. However...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Feb 2010

    Approximate Shortest Paths Avoiding a Failed Vertex : Optimal Size Data Structures for Unweighted Graphs

    The shortest paths problem is a classical and well studied algorithmic problem of computer science. This problem requires processing of a given graph G = (V,E) on n = |V | vertices and m = |E| edges to compute a data structure using which shortest path or distance between any...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Sep 2010

    An Application-Oriented Model for Wireless Sensor Networks Integrated With Telecom Infra

    This paper aims to propose a significant way of remote access and real time monitoring of a particular geographic area by integrating wireless sensor clouds with existing Telecom infrastructure and applications built around them through a gateway. This utility is very potent for environment monitoring in harsh and inaccessible places...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Apr 2011

    Security of Prime Field Pairing Cryptoprocessor Against Differential Power Attack

    This paper deals with the differential power attack on a pairing cryptoprocessor. The cryptoprocessor is designed for pairing computations on elliptic curves defined over finite fields with large prime characteristic. The paper pinpoints the vulnerabilities of such pairing computations against side-channel attacks. By exploiting the power consumptions, the paper experimentally...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Sep 2009

    Dynamically Generated Interfaces in XML Based Architecture

    Providing on-line services on the Internet will require the definition of flexible interfaces that are capable of adapting to the user's characteristics. This is all the more important in the context of medical applications like home monitoring, where no two patients have the same medical profile and yet, the same...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Aug 2010

    Multi-Algorithmic Iris Authentication System

    The paper proposes a novel technique for iris recognition using texture and phase features. Texture features are extracted on the normalized iris strip using Haar Wavelet while phase features are obtained using LOG Gabor Wavelet. The matching scores generated from individual modules are combined using sum of score technique. The...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2011

    A Routing Algorithm for Multi-Hop Mobile Ad-Hoc Networks Using Weighted Delaunay Triangulation

    A multi-hop mobile ad-hoc network is a collection of wireless mobile hosts forming a temporary network without the aid of any centralized administration or standard support services. In such an environment, it is necessary for each mobile node to act both as a host and as router. Such a network...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2011

    Feasibility Study of Spatial Reuse in an 802.11 Access Network

    Despite a decade and a half of communication revolution, much of the rural population in developing countries is yet to see its benefits. The underlying reason for this is that communication technology (wired and cellular) is value-priced for western markets. Thus these technologies have found widespread deployment in metropolitan pockets...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2011

    Revisiting MAC Design for an 802.11 Based Mesh Network

    This paper deals with an 802.11-based access network for rural villages. 802.11's CSMA/CA MAC is known to perform poorly in mesh networks. In this paper, the authors present the design of a novel MAC suited to a mesh network with outdoor, long-distance, point-to-point links. Multi-hop 802.11 networks are a topic...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2010

    Optical Modulation Schemes to Implement BB84 and B92 Protocols Using Frequency-Coding Method

    The authors discuss possible modulation schemes to implement BB84 and B92 quantum key distribution protocols using frequency-coding method. They derive time evolution of quantum states of light in a Mach-Zehnder interferometer based optical intensity modulator. They then show that Phase Modulator-Phase Modulator (PM-PM) combination can be used to implement the...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Jan 2010

    VHDL Implementation of Two-State Multiple Turbo Codes

    With increasing demand for different data rates and services for communication systems, reconfigurability is of utmost importance. Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the configuration bit stream. Low complexity turbo-like codes based on simple two-state trellis or simple graph...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Dec 2009

    Performance Analysis of Alamouti Scheme With Transmit Antenna Selection in MISO Systems

    Antenna Selection (AS) schemes in Space Time Coded Multiple Input Multiple Output (STC-MIMO) systems are well documented in the literature. Performance analysis of STC-MIMO systems with AS have appeared. With the motivation to reduce the complexity of AS criteria and the rate of feedback bits some sub optimum AS schemes...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Dec 2010

    Fractional Timing Offset and Channel Estimation in OFDM Systems Over Flat Fading Channels

    This paper addresses the estimation of fractional timing offset and channel response in Orthogonal Frequency Division Multiplexing (OFDM) systems. Timing offset and channel estimator is derived based on maximum likelihood criterion. Closed form Cramer Rao Bound (CRB) expressions for fractional timing offset and channel response are derived. They consider flat...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Dec 2010

    A 6 mW Low Noise Amplifier for 3.1-10.6 GHz UWB Application

    This paper presents a single stage Low-Noise Amplifier (LNA) using cascode topology for low-power UWB applications. Resistive feedback is used to obtain large bandwidth. The LNA achieves peak gain of 11.8 dB and noise figure varying from1.72 - 3.62 dB within the band of 3.1 - 10.6 GHz. The LNA...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Dec 2010

    Significance of the LP-MVDR Spectral Ratio Method in Whisper Detection

    A new spectral ratio method is proposed in this paper for detecting whispered segments within a normally phonated speech stream. The method is based on computing the ratio of the Linear Prediction(LP) spectrum to the Minimum Variance Distortion less Response (MVDR) spectrum. Both the linear prediction method and the LP...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Mar 2012

    Fractional Timing Offset and Channel Estimation for MIMO OFDM Systems Over Flat Fading Channels

    This paper addresses the problem of fractional timing offset and channel estimation in Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) systems. The estimators have been derived assuming a flat fading channel and using the maximum likelihood criterion. Closed form Cramer Rao Bound (CRB) expressions for fractional timing...

    Provided By Indian Institute of Technology Kanpur

  • White Papers // Feb 2012

    On the Optimality of Lattices for the Coppersmith Technique

    The authors investigate the Coppersmith technique for finding solutions of a univariate modular equation within a range given by range parameter U. This technique converts a given equation to an algebraic equation via a lattice reduction algorithm, and the choice of the lattice is crucial for the performance of the...

    Provided By Indian Institute of Technology Kanpur