Institute of Electrical & Electronic Engineers

Displaying 1-40 of 11069 results

  • White Papers // Apr 2014

    Cost-Effective Resource Provisioning for Mapreduce in a Cloud

    Cloud computing and its pay-as-you-go cost structure have enabled hardware infrastructure service providers, platform service providers as well as software and application service providers to offer computing services on demand and pay per use just like how the user use utility today. This growing trend in cloud computing, combined with...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2014

    FlexPRET: A Processor Platform for Mixed-Criticality Systems

    Mixed-criticality systems, in which multiple tasks of varying criticality execute on a single hardware platform, are an emerging research area in real-time embedded systems. High-criticality tasks require spatial and temporal isolation guarantees for independent verification, and the task set should efficiently utilize hardware resources. Hardware-based isolation is desirable but often...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2014

    Relaxing the Synchronous Approach for Mixed-Criticality Systems

    Safety-critical embedded systems are continuously superseded by more complex designs that must be certified against stringent safety-standards. Moreover, safety-measures must be incorporated to isolate and mitigate errors or faults that can develop at runtime. Mixed-criticality systems emerge when tasks with diverse levels of importance or criticality are integrated together. With...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2014

    WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores

    Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its ScratchPad Memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2014

    Towards Transcoding as a Service in Multimedia Cloud: Energy-Efficient Job Dispatching Algorithm

    In this paper, the authors investigate energy-efficient job dispatching algorithm for Transcoding-as-a-Service (TaaS) in a multimedia cloud. They aim to minimize the energy consumption of service engines in the cloud while achieving low delay for TaaS. They formulate the job dispatching problem as a constrained optimization problem under the framework...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2014

    Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip

    Photonic devices are widely used in Optical Networks-on-Chip (ONoCs) and suffer from crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the Signal-to-Noise Ratio (SNR), causes severe performance degradation, and constrains the network scalability. For the first time, this paper systematically analyzes and models the worst-case crosstalk noise...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Dynamic Request Redirection and Elastic Service Scaling in Cloud-Centric Media Networks

    The authors consider the problem of optimally redirecting user requests in a Cloud-Centric Media Network (CCMN) to multiple destination Virtual Machines (VMs), which elastically scale their service capacities in order to minimize a cost function that includes service response times, computing costs, and routing costs. They also allow the request...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    RC-Based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-Based 3D NoCs

    The Three-Dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems using die stacking in recent days. Because of the larger power density and the heterogeneous thermal conductance in different silicon layers of 3D NoC, the thermal problems of 3D NoC become more...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Main-Memory Hash Joins on Modern Processor Architectures

    Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Comparative Study of Characteristics of Traditional Database and Cloud Database: An Approach for Data Migration

    The information technology has grown tremendously during the last two decades and information sharing and exchange has been changed from standalone machine to networking, networking to internet, internet to cloud environment. The use of database in this context has also changed due to the business requirement and functionalities provided. In...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

    Optical Networks-on-Chip (ONoCs) have shown the potential to be substituted for electronic Network-on-Chips (NoCs) to bring substantially higher bandwidth and more efficient power consumption in both on- and off-chip communication. However, basic optical devices, which are the key components in constructing ONoCs, experience inevitable crosstalk noise and power loss; the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Distributed Kalman Filtering over Big Data: Analysis Through Large Deviations of Random Riccati Equations

    In this paper, the authors discuss the Modified Gossip Interactive Kalman Filtering (M-GIKF) for distributed estimation over potentially big data sets generated by a large dynamical system, in which each sensor observes only a portion of the large process, such that, if acting alone, no sensors can successfully resolve the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Provable Ownership of File in De-duplication Cloud Storage

    The rapid adoption of cloud services has propelled network data sharing and storage. Client-side deduplication is proposed to minimize bandwidth and space needed to upload and store duplicated data. The existing solutions, however, were recently found to be vulnerable to attacks that enable the attackers to get full access to...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2014

    Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors

    Single-ISA heterogeneous Chip Multi-Processor (CMP) is not only an attractive design paradigm but also is expected to occur as a consequence of manufacturing imperfections, such as process variation and permanent faults. Process variation could cause cores to have different maximum frequencies; whereas permanent faults could cause losses of functional units...

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  • White Papers // Jan 2014

    Evaluating Allocation Paradigms for Multi-Objective Adaptive Provisioning in Virtualized Networks

    Recent advances in virtualization technology have made it possible to partition a network into multiple virtual networks managed by different users. Although virtual networks share the same physical infrastructure, they host diverse applications with different goals. Unfortunately, current virtual network provisioning solutions have only focused on achieving a single objective...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems

    The regular topology of mesh-based Network-on-Chip (NoC) provides flexible and scalable architecture for Chip Multi-Processor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. In the field of Wide Area Networks (WANs), Ant Colony Optimization (ACO) has been applied to an adaptive routing for improving...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Protecting Your Right: Attribute-Based Keyword Search With Fine-Grained Owner-Enforced Search Authorization in the Cloud

    Search over encrypted data is a critically important enabling technique in cloud computing, where encryption-before-outsourcing is a fundamental solution to protecting user data privacy in the untrusted cloud server environment. Many secure search schemes have been focusing on the single-contributor scenario, where the outsourced dataset or the secure searchable index...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Venice: Reliable Virtual Data Center Embedding in Clouds

    Cloud computing has become a cost-effective model for deploying online services in recent years. To improve the Quality-of-Service (QoS) of the provisioned services, recently a number of proposals have advocated provisioning both guaranteed server and network resources in the form of Virtual Data Centers (VDCs). However, existing VDC scheduling algorithms...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Dynamic Pricing and Profit Maximization for the Cloud with Geo-distributed Data Centers

    Cloud providers often choose to operate datacenters over a large geographic span, in order that users may be served by resources in their proximity. Due to time and spatial diversities in utility prices and operational costs, different datacenters typically have disparate charges for the same services. Cloud users are free...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Privacy-Preserving Multi-Keyword Fuzzy Search over Encrypted Data in the Cloud

    Enabling keyword search directly over encrypted data is a desirable technique for effective utilization of encrypted data outsourced to the cloud. Existing solutions provide multi-keyword exact search that does not tolerate keyword spelling error, or single keyword fuzzy search that tolerates typos to certain extent. The current fuzzy search schemes...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Online Algorithms for Uploading Deferrable Big Data to The Cloud

    Cloud computing is emerging as a new computing paradigm that enables prompt and on-demand access to computing resources. As exemplified in Amazon EC2 and Linode, cloud providers invest substantially into their data centre infrastructure, providing a virtually unlimited \"Sea\" of CPU, RAM and bandwidth resources to cloud users, often assisted...

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  • White Papers // Jan 2014

    Dynamic Resource Provisioning in Cloud Computing: A Randomized Auction Approach

    The cloud computing paradigm offers users rapid on-demand access to computing resources such as CPU, RAM and storage, with minimal management overhead. Recent commercial cloud platforms, exemplified by Amazon EC2, Microsoft Azure and Linode, organize a shared resource pool for serving their users. Virtualization technologies help cloud providers pack their...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Lightweight Application-level Task Migration for Mobile Cloud Computing

    Mobile cloud computing allows mobile applications to use the enormous resources in the clouds. In order to seamlessly utilize the resources, it is common to migrate computation among mobile nodes and cloud nodes. Therefore, a highly portable and transparent migration approach is needed. In terms of portability, application-level migration with...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Dynamic Heterogeneity-Aware Resource Provisioning in the Cloud

    Data centers consume tremendous amounts of energy in terms of power distribution and cooling. Dynamic capacity provisioning is a promising approach for reducing energy consumption by dynamically adjusting the number of active machines to match resource demands. However, despite extensive studies of the problem, existing solutions have not fully considered...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Time-Series Pattern Based Effective Noise Generation for Privacy Protection on Cloud

    Cloud computing is proposed as an open and promising computing paradigm where customers can deploy and utilize IT services in a pay-as-you-go fashion while saving huge capital investment in their own IT infrastructure. Due to the openness and virtualization, various malicious service providers may exist in these cloud environments, and...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Capturing Inter-Application Interference on Clusters

    Cluster systems usually run several applications - often from different users - concurrently, with individual applications competing for access to shared resources such as the file system or the network. Low application performance is therefore not always the result of inefficient program design, but may instead be caused by interference...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Performance Boosting under Reliability and Power Constraints

    Voltage droops resulting from inductive noise are common in state-of-the-art processors. Many of the techniques used to reduce energy consumption - clock gating, power gating, process shrinks, and voltage reduction - lead to increased voltage droops or increased sensitivity to voltage variations. Designers use voltage guardbands to minimize errors due...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Improving Scalability of OpenMP Applications on Multi-Core Systems Using Large Page Support

    Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the Intel Xeon have the ability to run several threads on a single core. The OpenMP standard for compiler directive based shared memory programming allows...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2014

    Classifying Phishing Emails Using Confidence-Weighted Linear Classifiers

    Though Internet users are generally becoming more aware of phishing emails and phishing websites, cyber scammers are able to come up with novel schemes constantly that circumvent phishing filters and often succeed in fooling even savvy users. Using heuristic approaches and knowledge about the phishing techniques, researchers have developed several...

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  • White Papers // Jan 2014

    An Architecture for Automatic and Adaptive Defense

    Network attacks have become so fast that human mitigation does not cope with security requirements. In addition, attacks are done in a smarter way mutating itself to prevent detection. Therefore, defense mechanisms must be automatic to comply with attack speed and adaptive to comply with their mutation. An architecture to...

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  • White Papers // Jan 2014

    Designing Efficient Asynchronous Memory Operations Using Hardware Copy Engine: A Case Study with I/OAT

    Memory copies for bulk data transport incur large overheads due to CPU stalling, small register-size data movement, etc. Intel's I/O Acceleration Technology offers an asynchronous memory copy engine in kernel space which alleviates such overheads. In this paper, the authors propose a set of designs for asynchronous memory operations in...

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  • White Papers // Dec 2013

    Information Flow Control for Secure Cloud Computing

    Security concerns are widely seen as an obstacle to the adoption of cloud computing solutions. Information Flow Control (IFC) is a well understood Mandatory Access Control methodology. The earliest IFC models targeted security in a centralised environment, but decentralised forms of IFC have been designed and implemented, often within academic...

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  • White Papers // Dec 2013

    On Efficient Bandwidth Allocation for Traffic Variability in Datacenters

    Datacenter networks suffer unpredictable performance due to a lack of application level bandwidth guarantees. A lot of attentions have been drawn to solve this problem such as how to provide bandwidth guarantees for Virtualized Machines (VMs), proportional bandwidth share among tenants, and high network utilization under peak traffic. However, existing...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2013

    LD-Sketch: A Distributed Sketching Design for Accurate and Scalable Anomaly Detection in Network Data Streams

    Real-time characterization of traffic anomalies, such as heavy hitters and heavy changers, is critical for the robustness of operational networks, but its accuracy and scalability are challenged by the ever-increasing volume and diversity of network traffic. The authors address this problem by leveraging parallelization. They propose LD-Sketch, a data structure...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2013

    PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-Throughput Many-Core Systems-on-Chip

    Abstract - Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and Many-Core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint....

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  • White Papers // Dec 2013

    On the Delay-Storage Trade-Off in Content Download From Coded Distributed Storage Systems

    In this paper, the authors study how coding in distributed storage reduces expected downloads time, in addition to providing reliability against disk failures. The expected download time is reduced because when a content file is encoded to add redundancy and distributed across multiple disks, reading only a subset of the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2013

    New Repair Strategy of Hadamard Minimum Storage Regenerating Code for Distributed Storage System

    The newly presented (k+2, k) Hadamard Minimum Storage Regenerating (MSR) code is the first class of high rate storage code with optimal repair property for all single node failures. In this paper, the authors propose a new simple repair strategy, which can considerably reduces the computation load of the node...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2013

    Self-Tuning Batching With DVFS for Improving Performance and Energy Efficiency in Servers

    Performance improvement and energy efficiency are two important goals in provisioning Internet services in data center servers. In this paper, the authors propose and develop a self-tuning request batching mechanism to simultaneously achieve the two correlated goals. The batching mechanism increases the cache hit rate at the front-tier web server,...

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  • White Papers // Dec 2013

    Panda: Public Auditing for Shared Data with Efficient User Revocation in the Cloud

    With data storage and sharing services in the cloud, users can easily modify and share data as a group. To ensure shared data integrity can be verified publicly, users in the group need to compute signatures on all the blocks in shared data. Different blocks in shared data are generally...

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  • White Papers // Dec 2013

    Selective Interference Alignment for MIMO Cognitive Femtocell Networks

    This paper presents a novel cross-tier interference management solution for coexisting two-tier networks by exploiting cognition and coordination between tiers via the use of agile radios. The cognitive users sense their environment to determine the receivers they are interfering with, and adapt to it by designing their pre-coders using Interference...

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  • White Papers // Dec 2011

    An Optimizing Compiler for Out-of-Order Parallel ESL Simulation Exploiting Instance Isolation

    Electronic System-Level (ESL) design relies on fast Discrete Event (DE) simulation for the validation of design models written in System-Level Description Languages (SLDLs). An advanced technique to speedup ESL validation is out-of-order parallel DE simulation which allows multiple threads to run early and in parallel on multi-core hosts. To avoid...

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  • White Papers // Dec 2009

    A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models

    Embedded system design usually starts from an executable specification model described in a C-based System Level Description Language (SLDL), such as SystemC or SpecC. In this paper, the authors identify a subset of well-defined C-based design models, called periodic ConcurrenC models that can be statically scheduled, resulting in significant higher...

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  • White Papers // Oct 2008

    Automatic Verification of External Interrupt Behaviors for Microprocessor Design

    Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called Processor Exception Verification Tool (PEVT), to verify the...

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  • White Papers // Sep 2009

    Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors

    An In-Circuit Emulator (ICE) is part of the development environment for a microprocessor- or microcontroller-based system - called a target system. In-circuit emulators have become part of the permanent structure of microprocessor cores to support on-chip test and debug activities in highly integrated environments such as SoCs. However, ICE design...

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  • White Papers // Jul 2009

    A Trace-Capable Instruction Cache for Cost Efficient Real-Time Program Trace Compression in SoC

    In this paper the authors present a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor, named Trace-Capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with...

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  • White Papers // Apr 2011

    An On-Chip AHB Bus Tracer with Real-Time Compression and Dynamic Multiresolution Supports for SoC

    In this paper the authors propose a multi-resolution AHB on-chip bus tracer named SYS-HMRBT (aHb Multi-Resolution Bus Tracer) for versatile System-on-Chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2008

    Automatic Re-Coding of Reference Code Into Structured and Analyzable SoC Models

    The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are effective in generating efficient implementations. However, readily available reference C codes are not conducive for the system synthesis as they lack...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2008

    Automatic Generation of Hardware Dependent Software for MPSoCs From Abstract System Specifications

    Increasing software content in embedded systems and SoCs drives the demand to automatically synthesize software binaries from abstract models. This is especially critical for Hardware dependent Software (HdS) due to the tight coupling. In this paper, the authors present their approach to automatically synthesize HdS from an abstract system model....

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  • White Papers // Dec 2010

    Multi-Core Parallel Simulation of System-Level Description Languages

    The validation of transaction level models described in System-Level Description Languages (SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) simulation of SLDLs is cooperative and cannot utilize the available parallelism in modern multi-core CPU hosts. In this paper, the authors study the SLDL execution semantics of concurrent...

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  • White Papers // May 2010

    ESL Design and Multi-Core Validation Using the System-on-Chip Environment

    Design at the Electronic System-Level (ESL) tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Aiming at an automated top-down synthesis flow, effective ESL design frameworks are needed in transforming and refining the high-level design models until a satisfactory Multi-Processor System-on-Chip...

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  • White Papers // Dec 2009

    System-Level Development of Embedded Software

    Embedded software plays an increasingly important role in implementing modern embedded systems. Development of embedded software and of hardware-dependent software in particular, is challenging due to the tight integration with the underlying hardware architecture. In this paper, the authors describe their system-level design approach that allows designers to develop software...

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  • White Papers // Dec 2009

    Computer-Aided Recoding for Multi-Core Systems

    The design of embedded computing systems faces a serious productivity gap due to the increasing complexity of their hardware and software components. One solution to address this problem is the modeling at higher levels of abstraction. However, manually writing proper executable system models is challenging, error-prone, and very time-consuming. The...

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  • White Papers // Dec 2008

    An 8.69 Mvertices/s 278 Mpixels/s Tile-Based 3D Graphics SoC HW/SW Development for Consumer Electronics

    Recently, the 3D Graphics (3DG) applications have fast growth on consumer electronics due to the consumers' requirements. There are many features of consumer electronics which are quite different from that developed in traditional 3DG for workstation or desktop PC's. This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based...

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  • White Papers // Sep 2009

    A Reverse-Encoding-Based On-Chip AHB Bus Tracer for Efficient Circular Buffer Utilization

    The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus, makes it...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2009

    An Efficient HW/SW Integrated Verification Methodology for 3D Graphics SoC Development

    In this paper the authors propose an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification...

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  • White Papers // Dec 2009

    An Embedded Debugging/Performance Monitoring Engine for a Tile-Based 3D Graphics SoC Development

    Recently, the 3D Graphics (3DG) applications have become increasingly popular for consumer electronics, especially, the market for 3DG gaming application on mobile devices. Such consumer electronics are quite different from the workstations and desktop PCs for which traditional 3DG applications were first developed. This paper presents an Embedded Debugging/ Performance...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2007

    A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors

    Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real-time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2009

    The Development of an Energy-Awared Mobile 3D Graphics SoC with Real-Time Performance/Energy Monitoring and Control

    Portable mobile computing and communication applications demand low-power and low-energy with high performance. These competing demands drive SoC development. Especially, 3D graphics-intensive applications are predicted to become widely available on a variety of portable mobile devices ranging from laptops to PDAs to mobile phones. Such 3D graphics coprocessors were originally...

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  • White Papers // Sep 2009

    Verifying External Interrupts of Embedded Microprocessor in SoC with On-Chip Bus

    The microprocessor verification challenge becomes higher in the On-Chip Bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. In this paper the authors propose an automatic method to verify the...

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  • White Papers // Dec 2006

    An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools

    Embedded microprocessors are divided into 3 categories: 8-bit, 16-bit and 32-bit microprocessor, depending on the demand of performance, cost, power, and programmability. For simple control system which requires extremely low cost and low power, 8-bit microprocessor is the best choice. A 16-bit THUMB instruction set microprocessor is proposed for low...

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  • White Papers // May 2013

    Efficient Partitioning of Sporadic Real-Time Tasks with Shared Resources and Spin Locks

    Partitioned fixed-priority scheduling is widely used in embedded multiprocessor real-time systems due to its simplicity and low runtime overheads. However, it fundamentally requires a static mapping of tasks to processors to be determined. Optimal task set partitioning is known to be NP-hard, and the situation is further aggravated when limited...

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  • White Papers // Apr 2008

    AMBA AHB Bus Potocol Checker with Efficient Debugging Mechanism

    Bus-based System-on-Chip (SoC) design becomes the major integration methods for shorting design cycle and time-to-market, thus how to verify IP functionality on bus protocol is a challenge. Traditional simulation-based bus protocol monitors can check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms. The...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Oct 2008

    NCPA: A Scheduling Algorithm for Multi-Cipher and Multi-Mode Reconfigurable Cryptosystem

    Multi-cipher and multi-mode reconfigurable cryptosystems are widely used for hardware acceleration in modern security protocols, such as SSL and IPsec, but there has been hardly any work which can process multiple cipher algorithms with varied block lengths, key lengths and operation modes at a session of communication owing to the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2008

    Parameterized Embedded In-Circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor

    An In-Circuit Emulator (ICE) is part of the development environment for microprocessor (or microcontroller)-based systems (called target systems). The In-Circuit Emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Nov 2009

    Integrated Management of Application Performance, Power and Cooling in Data Centers

    Data centers contain IT, power and cooling infrastructures, each of which is typically managed independently. In this paper, the authors propose a holistic approach that couples the management of IT, power and cooling infrastructures to improve the efficiency of data center operations. Their approach considers application performance management, dynamic workload...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2010

    Automated Synthesis of Sustainable Data Centers

    Next generation data centers must be designed to meet Service Level Agreements (SLAs) for application performance while reducing costs and environmental impact. Traditional design approaches are manually intensive and must integrate thousands of components at multiple granularities, often with conflicting goals. The authors propose an automated data center synthesizer to...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Oct 2007

    Data Placement for Scientific Applications in Distributed Environments

    Scientific applications often perform complex computational analyses that consume and produce large data sets. The authors are concerned with data placement policies that distribute data in ways that are advantageous for application execution, for example, by placing data sets so that they may be staged into or out of computations...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Sep 2010

    SAMR: A Self-adaptive MapReduce Scheduling Algorithm In Heterogeneous Environment

    Hadoop is seriously limited by its MapReduce scheduler who does not scale well in heterogeneous environment. Heterogenous environment is characterized by various devices which vary greatly with respect to the capacities of computation and communication, architectures, memorizes and power. As an important extension of Hadoop, LATE MapReduce scheduling algorithm takes...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Feb 2010

    Robust Data Placement in Urgent Computing Environments

    Distributed urgent computing workflows often require data to be staged between multiple computational resources. Since these workflows execute in shared computing environments where users compete for resource usage, it is necessary to allocate resources that can meet the deadlines associated with time-critical workflows and can tolerate interference from other users....

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  • White Papers // Jun 2013

    Parallel Consensus is Harder than Set Agreement in Message Passing

    In the traditional consensus task, processes are required to agree on a common value chosen among the initial values of the participating processes. It is well known that consensus cannot be solved in crash-prone, asynchronous distributed systems. Two generalizations of the consensus tasks have been introduced: k-set agreement and k-parallel...

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  • White Papers // Jun 2013

    Safety of Deferred Update in Transactional Memory

    Transactional memory allows the user to declare sequences of instructions as speculative transactions that can either commit or abort. If a transaction commits, it appears to be executed sequentially, so that the committed transactions constitute a correct sequential execution. If a transaction aborts, none of its instructions can affect other...

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  • White Papers // Jun 2013

    On the k-Atomicity-Verification Problem

    Data consistency is an important consideration in storage systems. Modern Internet-scale storage systems often provide weak (rather than strong) consistency in exchange for better performance and resilience. An important weak consistency property is k-atomicity. A history of operations is called k-atomic iff there exists a valid total order on the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    On Server Provisioning for Distributed Interactive Applications

    Benefiting from the rapid growth of Internet technologies, an increasing number of Distributed Interactive Applications (DIAs) are emerging to provide people with new ways of collaboration and entertainment. In these applications, participants dispersed at different locations interact with each other through the network in real time. Increasing geographical spreads of...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    Ripple: Improved Architecture and Programming Model for Bulk Synchronous Parallel Style of Analytics

    The authors present Ripple, an architecture and a programming model for a broad set of data analytics. Ripple builds on the ideas of iterated MapReduce and adds two innovations. First it has a richer programming model, including more ideas from the Bulk Synchronous Parallel (BSP) model of computation and others....

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Aug 2011

    VirtPerf: A Performance Profiling Tool for Virtualized Environments

    Several applications in the \"Physical\" world are being consolidated in \"Virtual\" environments using different virtualization technologies. An important criterion for this exercise is to understand potential resource requirements and performance levels achieved in virtual environments. Empirical evidence of these can be gotten by benchmarking the application's performance in a controlled...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    Efficient Geo-Distributed Data Processing with Rout

    Big data processing undoubtedly represents one of the major challenges of this era. Indeed, the current limitations of many applications in healthcare, science, commerce, government, or finance alike are dictated by the amount of data that can be analyzed or processed in a given timeframe. While hardware dictates certain fundamental...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    Present or Future: Optimal Pricing for Spot Instances

    The recent years witnessed rapid emergence and proliferation of cloud computing. To fully utilize the compute resources, some cloud operators provide spot resources. Spot resources allow customers to bid on unused capacity. However, pricing policy of spot resources should be carefully designed and the impact on both present and future...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    Ease the Queue Oscillation: Analysis and Enhancement of DCTCP

    Because of the terrible performance of TCP protocol in data center environment, DCTCP has been proposed as a TCP replacement, which uses a simple marking mechanism at switches and a few amendments at end hosts to adjust congestion window based on the extent of the congestion in networks. Thus, DCTCP...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    RBFT: Redundant Byzantine Fault Tolerance

    Byzantine Fault Tolerant (BFT) state machine replication protocols are replication protocols that tolerate arbitrary faults of a fraction of the replicas. Although significant efforts have been recently made, existing BFT protocols do not provide acceptable performance when faults occur. As the authors show in this paper, this comes from the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2013

    ImageElves: Rapid and Reliable System Updates in the Cloud

    Virtualization has significantly reduced the cost of creating a new virtual machine and cheap storage allows VMs to be turned down when unused. This has led to a rapid proliferation of virtual machine images, both active and dormant, in the data center. System management technologies have not been able to...

    Provided By Institute of Electrical & Electronic Engineers