Institute of Electrical & Electronic Engineers

Displaying 1-40 of 10979 results

  • White Papers // Apr 2014

    FlexPRET: A Processor Platform for Mixed-Criticality Systems

    Mixed-criticality systems, in which multiple tasks of varying criticality execute on a single hardware platform, are an emerging research area in real-time embedded systems. High-criticality tasks require spatial and temporal isolation guarantees for independent verification, and the task set should efficiently utilize hardware resources. Hardware-based isolation is desirable but often...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2014

    Relaxing the Synchronous Approach for Mixed-Criticality Systems

    Safety-critical embedded systems are continuously superseded by more complex designs that must be certified against stringent safety-standards. Moreover, safety-measures must be incorporated to isolate and mitigate errors or faults that can develop at runtime. Mixed-criticality systems emerge when tasks with diverse levels of importance or criticality are integrated together. With...

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  • White Papers // Apr 2014

    WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores

    Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its ScratchPad Memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques...

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  • White Papers // Mar 2014

    Towards Transcoding as a Service in Multimedia Cloud: Energy-Efficient Job Dispatching Algorithm

    In this paper, the authors investigate energy-efficient job dispatching algorithm for Transcoding-as-a-Service (TaaS) in a multimedia cloud. They aim to minimize the energy consumption of service engines in the cloud while achieving low delay for TaaS. They formulate the job dispatching problem as a constrained optimization problem under the framework...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2014

    Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip

    Photonic devices are widely used in Optical Networks-on-Chip (ONoCs) and suffer from crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the Signal-to-Noise Ratio (SNR), causes severe performance degradation, and constrains the network scalability. For the first time, this paper systematically analyzes and models the worst-case crosstalk noise...

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  • White Papers // Feb 2014

    Dynamic Request Redirection and Elastic Service Scaling in Cloud-Centric Media Networks

    The authors consider the problem of optimally redirecting user requests in a Cloud-Centric Media Network (CCMN) to multiple destination Virtual Machines (VMs), which elastically scale their service capacities in order to minimize a cost function that includes service response times, computing costs, and routing costs. They also allow the request...

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  • White Papers // Feb 2014

    RC-Based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-Based 3D NoCs

    The Three-Dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems using die stacking in recent days. Because of the larger power density and the heterogeneous thermal conductance in different silicon layers of 3D NoC, the thermal problems of 3D NoC become more...

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  • White Papers // Feb 2014

    Main-Memory Hash Joins on Modern Processor Architectures

    Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that...

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  • White Papers // Feb 2014

    Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

    Optical Networks-on-Chip (ONoCs) have shown the potential to be substituted for electronic Network-on-Chips (NoCs) to bring substantially higher bandwidth and more efficient power consumption in both on- and off-chip communication. However, basic optical devices, which are the key components in constructing ONoCs, experience inevitable crosstalk noise and power loss; the...

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  • White Papers // Feb 2014

    Comparative Study of Characteristics of Traditional Database and Cloud Database: An Approach for Data Migration

    The information technology has grown tremendously during the last two decades and information sharing and exchange has been changed from standalone machine to networking, networking to internet, internet to cloud environment. The use of database in this context has also changed due to the business requirement and functionalities provided. In...

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  • White Papers // Feb 2014

    Distributed Kalman Filtering over Big Data: Analysis Through Large Deviations of Random Riccati Equations

    In this paper, the authors discuss the Modified Gossip Interactive Kalman Filtering (M-GIKF) for distributed estimation over potentially big data sets generated by a large dynamical system, in which each sensor observes only a portion of the large process, such that, if acting alone, no sensors can successfully resolve the...

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  • White Papers // Feb 2014

    Provable Ownership of File in De-duplication Cloud Storage

    The rapid adoption of cloud services has propelled network data sharing and storage. Client-side deduplication is proposed to minimize bandwidth and space needed to upload and store duplicated data. The existing solutions, however, were recently found to be vulnerable to attacks that enable the attackers to get full access to...

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  • White Papers // Jan 2014

    Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems

    The regular topology of mesh-based Network-on-Chip (NoC) provides flexible and scalable architecture for Chip Multi-Processor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. In the field of Wide Area Networks (WANs), Ant Colony Optimization (ACO) has been applied to an adaptive routing for improving...

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  • White Papers // Jan 2014

    Lightweight Application-level Task Migration for Mobile Cloud Computing

    Mobile cloud computing allows mobile applications to use the enormous resources in the clouds. In order to seamlessly utilize the resources, it is common to migrate computation among mobile nodes and cloud nodes. Therefore, a highly portable and transparent migration approach is needed. In terms of portability, application-level migration with...

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  • White Papers // Jan 2014

    Capturing Inter-Application Interference on Clusters

    Cluster systems usually run several applications - often from different users - concurrently, with individual applications competing for access to shared resources such as the file system or the network. Low application performance is therefore not always the result of inefficient program design, but may instead be caused by interference...

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  • White Papers // Jan 2014

    Improving Scalability of OpenMP Applications on Multi-Core Systems Using Large Page Support

    Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the Intel Xeon have the ability to run several threads on a single core. The OpenMP standard for compiler directive based shared memory programming allows...

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  • White Papers // Jan 2014

    Classifying Phishing Emails Using Confidence-Weighted Linear Classifiers

    Though Internet users are generally becoming more aware of phishing emails and phishing websites, cyber scammers are able to come up with novel schemes constantly that circumvent phishing filters and often succeed in fooling even savvy users. Using heuristic approaches and knowledge about the phishing techniques, researchers have developed several...

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  • White Papers // Jan 2014

    An Architecture for Automatic and Adaptive Defense

    Network attacks have become so fast that human mitigation does not cope with security requirements. In addition, attacks are done in a smarter way mutating itself to prevent detection. Therefore, defense mechanisms must be automatic to comply with attack speed and adaptive to comply with their mutation. An architecture to...

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  • White Papers // Jan 2014

    Designing Efficient Asynchronous Memory Operations Using Hardware Copy Engine: A Case Study with I/OAT

    Memory copies for bulk data transport incur large overheads due to CPU stalling, small register-size data movement, etc. Intel's I/O Acceleration Technology offers an asynchronous memory copy engine in kernel space which alleviates such overheads. In this paper, the authors propose a set of designs for asynchronous memory operations in...

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  • White Papers // Dec 2013

    Information Flow Control for Secure Cloud Computing

    Security concerns are widely seen as an obstacle to the adoption of cloud computing solutions. Information Flow Control (IFC) is a well understood Mandatory Access Control methodology. The earliest IFC models targeted security in a centralised environment, but decentralised forms of IFC have been designed and implemented, often within academic...

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  • White Papers // Dec 2013

    On Efficient Bandwidth Allocation for Traffic Variability in Datacenters

    Datacenter networks suffer unpredictable performance due to a lack of application level bandwidth guarantees. A lot of attentions have been drawn to solve this problem such as how to provide bandwidth guarantees for Virtualized Machines (VMs), proportional bandwidth share among tenants, and high network utilization under peak traffic. However, existing...

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  • White Papers // Dec 2013

    LD-Sketch: A Distributed Sketching Design for Accurate and Scalable Anomaly Detection in Network Data Streams

    Real-time characterization of traffic anomalies, such as heavy hitters and heavy changers, is critical for the robustness of operational networks, but its accuracy and scalability are challenged by the ever-increasing volume and diversity of network traffic. The authors address this problem by leveraging parallelization. They propose LD-Sketch, a data structure...

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  • White Papers // Dec 2013

    PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-Throughput Many-Core Systems-on-Chip

    Abstract - Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and Many-Core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint....

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  • White Papers // Dec 2013

    On the Delay-Storage Trade-Off in Content Download From Coded Distributed Storage Systems

    In this paper, the authors study how coding in distributed storage reduces expected downloads time, in addition to providing reliability against disk failures. The expected download time is reduced because when a content file is encoded to add redundancy and distributed across multiple disks, reading only a subset of the...

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  • White Papers // Dec 2013

    New Repair Strategy of Hadamard Minimum Storage Regenerating Code for Distributed Storage System

    The newly presented (k+2, k) Hadamard Minimum Storage Regenerating (MSR) code is the first class of high rate storage code with optimal repair property for all single node failures. In this paper, the authors propose a new simple repair strategy, which can considerably reduces the computation load of the node...

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  • White Papers // Dec 2013

    Self-Tuning Batching With DVFS for Improving Performance and Energy Efficiency in Servers

    Performance improvement and energy efficiency are two important goals in provisioning Internet services in data center servers. In this paper, the authors propose and develop a self-tuning request batching mechanism to simultaneously achieve the two correlated goals. The batching mechanism increases the cache hit rate at the front-tier web server,...

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  • White Papers // Dec 2013

    Panda: Public Auditing for Shared Data with Efficient User Revocation in the Cloud

    With data storage and sharing services in the cloud, users can easily modify and share data as a group. To ensure shared data integrity can be verified publicly, users in the group need to compute signatures on all the blocks in shared data. Different blocks in shared data are generally...

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  • White Papers // Dec 2013

    Selective Interference Alignment for MIMO Cognitive Femtocell Networks

    This paper presents a novel cross-tier interference management solution for coexisting two-tier networks by exploiting cognition and coordination between tiers via the use of agile radios. The cognitive users sense their environment to determine the receivers they are interfering with, and adapt to it by designing their pre-coders using Interference...

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  • White Papers // Dec 2013

    Analysis of a Password Strengthening Technique and its Practical Use

    Besides commonly used password strengthening techniques such as salting or repeated applications of a one way function on the password, the users' account a less common procedure: the truncation of the output from a one-way function on the password. This technique is used in a Norwegian ATM and a similar...

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  • White Papers // Dec 2013

    Decision Support for the Migration of the Application Database Layer to the Cloud

    Migrating an existing application to the cloud is a complex and multi-dimensional problem requiring in many cases adapting the application in significant ways. Looking specifically into the database layer of the application, i.e. the aspect providing data persistence and manipulation capabilities, this involves dealing with differences in the granularity of...

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  • White Papers // Dec 2013

    Spatial-Temporal Enhancement of ACO-based Selection Schemes for Adaptive Routing in Network-on-Chip Systems

    Networks-on-Chip (NoC) provides regular and scalable design architecture for Chip Multi-Processor (CMP) systems. The Ant Colony Optimization (ACO) is a distributed algorithm. Applying ACO to selection models of adaptive routing can improve NoC performance. Currently, ACO-based selection only uses the historical traffic information. While additional temporal and spatial information provides...

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  • White Papers // Dec 2013

    Redundancy and Aging of Efficient Multidimensional MDS-Parity Protected Distributed Storage Systems

    The effect of redundancy on the aging of an efficient Maximum Distance Separable (MDS) parity - protected distributed storage system that consists of multidimensional arrays of storage units is explored. In light of the experimental evidences and survey data, this paper develops generalized expressions for the reliability of array storage...

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  • White Papers // Dec 2013

    Secure On-Off Transmission Design With Channel Estimation Errors

    Physical layer security has recently been regarded as an emerging technique to complement and improve the communication security in future wireless networks. The current research and development in physical layer security are often based on the ideal assumption of perfect channel knowledge or the capability of variable-rate transmissions. In this...

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  • White Papers // Dec 2013

    Moving Big Data to The Cloud: An Online Cost-Minimizing Approach

    Cloud computing, rapidly emerging as a new computation paradigm, provides agile and scalable resource access in a utility-like fashion, especially for the processing of big data. An important open issue here is to efficiently move the data, from different geographical locations over time, into a cloud for effective processing. The...

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  • White Papers // Nov 2013

    Proactive Thermal-Budget-Based Beltway Routing Algorithm for Thermal-Aware 3D NoC Systems

    The thermal problems of Three-Dimensional Network-on-Chip (3D NoC) systems become more serious because of die stacking. Besides, for high-performance requirement, the minimal adaptive routing algorithms result in unbalanced traffic load and worse temperature distribution in the system. On the other hand, the conventional selection strategies determine the routing path based...

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  • White Papers // Nov 2013

    SOCCA: A Security-Oriented Cyber-Physical Contingency Analysis in Power Infrastructures

    Contingency analysis is a critical activity in the context of the power infrastructure because it provides a guide for resiliency and enables the grid to continue operating even in the case of failure. In this paper, the authors augment this concept by introducing SOCCA, a cyber-physical security evaluation technique to...

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  • White Papers // Nov 2013

    A Tunable Version Control System for Virtual Machines in an Open-Source Cloud

    Open-source cloud platforms provide a feasible alternative of deploying cloud computing in low-cost commodity hardware and operating systems. To enhance the reliability of an open-source cloud, the authors design and implement CloudVS, a practical add-on system that enables version control for Virtual Machines (VMs). CloudVS targets a commodity cloud platform...

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  • White Papers // Nov 2013

    Collaborative Policy Administration

    Policy-based management is a very effective method to protect sensitive information. However, the over-claim of privileges is widespread in emerging applications, including mobile applications and social network services, because the applications' users involved in policy administration have little knowledge of policy-based management. The over-claim can be leveraged by malicious applications,...

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  • White Papers // Nov 2013

    Cloud Compute-and-Forward Relaying With Game-Theoretic Network Management

    Motivated by the challenges in the design and implementation of wireless cloud networks and the complex optimization of Physical layer Network Coding (PNC) in Compute-and-Forward (C&F) relaying, the authors propose a cooperative network management scheme for cloud C&F networks, employing coalitional game theory. The proposed scheme is an efficient PNC...

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  • White Papers // Nov 2013

    Degrees of Freedom of the Single Antenna Gaussian Wiretap Channel with a Helper Irrespective of the Number of Antennas at the Eavesdropper

    The wiretap channel model in provides the foundation for exploiting noisy communication channels to secure information at the physical layer. Specifically, Wyner in has established the secrecy capacity for a channel with one sender, one receiver, and one eavesdropper assuming that the received signal at the eavesdropper is a degraded...

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  • White Papers // Dec 2009

    Chip Multiprocessor Design Space Exploration through Statistical Simulation

    Developing fast Chip Multi-Processor (CMP) simulation techniques is a challenging problem. Solving this problem is especially valuable for design space exploration purposes during the early stages of the design cycle where a large number of design points need to be evaluated quickly. This paper studies statistical simulation as a fast...

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  • White Papers // Oct 2006

    Optimization of Signal Processing Software for Control System Implementation

    Signal processing plays a fundamental role in the design of control systems - the portion of a digitally-implemented control system between the sensor outputs and the actuator inputs is precisely a Digital Signal Processor (DSP). Consequently, effective techniques for design and optimization of signal processing software are important in achieving...

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  • White Papers // Oct 2007

    Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems

    When a data processing system consists of multiple computing units that run in parallel, their mutual communication needs to be synchronized in some manner to keep the results consistent. In this paper, the authors present four scheduling algorithms that provide flexible utilization of fine-grain DSP accelerators with low run-time overhead....

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  • White Papers // Oct 2010

    Exploring SW Performance Using Preemptive RTOS Models

    With increasing SW content of modern System-on-Chip (SoC) designs, modeling of embedded SW has become critical. For one, analyzing software performance early in the system design flow is now paramount to an efficient implementation. Previous work addressed performance modeling with timing annotated functional models and exposed dynamic scheduling effects with...

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  • White Papers // Oct 2012

    Eliminating Race Conditions in System-Level Models by Using Parallel Simulation Infrastructure

    For a top-down system design flow, a well-written specification model of an embedded system is crucial for its successful design and implementation. However, the task of writing a correct system-level model is difficult, as it involves, among other tasks, the insertion of parallelism. In this paper, the authors focus on...

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  • White Papers // Dec 2011

    Parallel Discrete Event Simulation of Transaction Level Models

    Describing Multi-Processor Systems-on-Chip (MPSoC) at the abstract Electronic System Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate system-level simulation is critical. Recently, Parallel Discrete Event Simulation (PDES) has gained significant attraction again as it promises to utilize the existing parallelism in today's multi-core CPU...

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  • White Papers // Nov 2006

    Register File Partitioning with Constraint Programming

    Highly parallel processors call for high bandwidth register access. One solution is to use multi-port register files. However, such register files are expensive in terms of chip area and their access time can lower the maximum clock frequency of the processor. Therefore, partitioning the multi-port register file to several smaller...

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  • White Papers // Feb 2006

    Contention-Conscious Transaction Ordering in Multiprocessor DSP Systems

    In this paper, the authors explore the problem of efficiently ordering Inter-Processor Communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most Digital Signal Processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic...

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  • White Papers // Jul 2006

    Efficient Techniques for Clustering and Scheduling Onto Embedded Multiprocessors

    Multiprocessor mapping and scheduling algorithms have been extensively studied over the past few decades and have been tackled from different perspectives. In the late 1980's, the two-step decomposition of scheduling - into clustering and cluster scheduling - was introduced. Ever since, several clustering and merging algorithms have been proposed and...

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  • White Papers // Nov 2009

    Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis

    In this paper, the authors present an in-depth case study on dataflow-based analysis and exploitation of parallelism in the design and implementation of a MPEG reconfigurable video coding decoder. Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as applications for multimedia processing...

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  • White Papers // Sep 2010

    Methods for Efficient Implementation of Model Predictive Control on Multiprocessor Systems

    Model Predictive Control (MPC) has been used in a wide range of application areas including chemical engineering, food processing, automotive engineering, aerospace, and metallurgy. An important limitation on the application of MPC is the difficulty in completing the necessary computations within the sampling interval. Recent trends in computing hardware towards...

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  • White Papers // Jan 2008

    Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces

    Microprocessor design is both complex and time consuming: Exploring a huge design space for identifying the optimal design under a number of constraints is infeasible using detailed architectural simulation of entire benchmark executions. Statistical simulation is a recently introduced approach for efficiently culling the microprocessor design space. The basic idea...

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  • White Papers // Dec 2009

    A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models

    Embedded system design usually starts from an executable specification model described in a C-based System Level Description Language (SLDL), such as SystemC or SpecC. In this paper, the authors identify a subset of well-defined C-based design models, called periodic ConcurrenC models that can be statically scheduled, resulting in significant higher...

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  • White Papers // Oct 2008

    Automatic Verification of External Interrupt Behaviors for Microprocessor Design

    Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called Processor Exception Verification Tool (PEVT), to verify the...

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  • White Papers // Sep 2009

    Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors

    An In-Circuit Emulator (ICE) is part of the development environment for a microprocessor- or microcontroller-based system - called a target system. In-circuit emulators have become part of the permanent structure of microprocessor cores to support on-chip test and debug activities in highly integrated environments such as SoCs. However, ICE design...

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  • White Papers // Jul 2009

    A Trace-Capable Instruction Cache for Cost Efficient Real-Time Program Trace Compression in SoC

    In this paper the authors present a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor, named Trace-Capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with...

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  • White Papers // Apr 2011

    An On-Chip AHB Bus Tracer with Real-Time Compression and Dynamic Multiresolution Supports for SoC

    In this paper the authors propose a multi-resolution AHB on-chip bus tracer named SYS-HMRBT (aHb Multi-Resolution Bus Tracer) for versatile System-on-Chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of...

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  • White Papers // Jan 2008

    Automatic Re-Coding of Reference Code Into Structured and Analyzable SoC Models

    The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are effective in generating efficient implementations. However, readily available reference C codes are not conducive for the system synthesis as they lack...

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  • White Papers // Jan 2008

    Automatic Generation of Hardware Dependent Software for MPSoCs From Abstract System Specifications

    Increasing software content in embedded systems and SoCs drives the demand to automatically synthesize software binaries from abstract models. This is especially critical for Hardware dependent Software (HdS) due to the tight coupling. In this paper, the authors present their approach to automatically synthesize HdS from an abstract system model....

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  • White Papers // Dec 2010

    Multi-Core Parallel Simulation of System-Level Description Languages

    The validation of transaction level models described in System-Level Description Languages (SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) simulation of SLDLs is cooperative and cannot utilize the available parallelism in modern multi-core CPU hosts. In this paper, the authors study the SLDL execution semantics of concurrent...

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  • White Papers // May 2010

    ESL Design and Multi-Core Validation Using the System-on-Chip Environment

    Design at the Electronic System-Level (ESL) tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Aiming at an automated top-down synthesis flow, effective ESL design frameworks are needed in transforming and refining the high-level design models until a satisfactory Multi-Processor System-on-Chip...

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  • White Papers // Dec 2009

    System-Level Development of Embedded Software

    Embedded software plays an increasingly important role in implementing modern embedded systems. Development of embedded software and of hardware-dependent software in particular, is challenging due to the tight integration with the underlying hardware architecture. In this paper, the authors describe their system-level design approach that allows designers to develop software...

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  • White Papers // Dec 2009

    Computer-Aided Recoding for Multi-Core Systems

    The design of embedded computing systems faces a serious productivity gap due to the increasing complexity of their hardware and software components. One solution to address this problem is the modeling at higher levels of abstraction. However, manually writing proper executable system models is challenging, error-prone, and very time-consuming. The...

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  • White Papers // Dec 2006

    An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools

    Embedded microprocessors are divided into 3 categories: 8-bit, 16-bit and 32-bit microprocessor, depending on the demand of performance, cost, power, and programmability. For simple control system which requires extremely low cost and low power, 8-bit microprocessor is the best choice. A 16-bit THUMB instruction set microprocessor is proposed for low...

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  • White Papers // May 2013

    Efficient Partitioning of Sporadic Real-Time Tasks with Shared Resources and Spin Locks

    Partitioned fixed-priority scheduling is widely used in embedded multiprocessor real-time systems due to its simplicity and low runtime overheads. However, it fundamentally requires a static mapping of tasks to processors to be determined. Optimal task set partitioning is known to be NP-hard, and the situation is further aggravated when limited...

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  • White Papers // Apr 2008

    AMBA AHB Bus Potocol Checker with Efficient Debugging Mechanism

    Bus-based System-on-Chip (SoC) design becomes the major integration methods for shorting design cycle and time-to-market, thus how to verify IP functionality on bus protocol is a challenge. Traditional simulation-based bus protocol monitors can check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms. The...

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  • White Papers // Oct 2008

    NCPA: A Scheduling Algorithm for Multi-Cipher and Multi-Mode Reconfigurable Cryptosystem

    Multi-cipher and multi-mode reconfigurable cryptosystems are widely used for hardware acceleration in modern security protocols, such as SSL and IPsec, but there has been hardly any work which can process multiple cipher algorithms with varied block lengths, key lengths and operation modes at a session of communication owing to the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jan 2008

    Parameterized Embedded In-Circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor

    An In-Circuit Emulator (ICE) is part of the development environment for microprocessor (or microcontroller)-based systems (called target systems). The In-Circuit Emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator...

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  • White Papers // Dec 2008

    An 8.69 Mvertices/s 278 Mpixels/s Tile-Based 3D Graphics SoC HW/SW Development for Consumer Electronics

    Recently, the 3D Graphics (3DG) applications have fast growth on consumer electronics due to the consumers' requirements. There are many features of consumer electronics which are quite different from that developed in traditional 3DG for workstation or desktop PC's. This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Sep 2009

    A Reverse-Encoding-Based On-Chip AHB Bus Tracer for Efficient Circular Buffer Utilization

    The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus, makes it...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Apr 2009

    An Efficient HW/SW Integrated Verification Methodology for 3D Graphics SoC Development

    In this paper the authors propose an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2009

    An Embedded Debugging/Performance Monitoring Engine for a Tile-Based 3D Graphics SoC Development

    Recently, the 3D Graphics (3DG) applications have become increasingly popular for consumer electronics, especially, the market for 3DG gaming application on mobile devices. Such consumer electronics are quite different from the workstations and desktop PCs for which traditional 3DG applications were first developed. This paper presents an Embedded Debugging/ Performance...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2007

    A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors

    Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real-time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This...

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  • White Papers // Apr 2009

    The Development of an Energy-Awared Mobile 3D Graphics SoC with Real-Time Performance/Energy Monitoring and Control

    Portable mobile computing and communication applications demand low-power and low-energy with high performance. These competing demands drive SoC development. Especially, 3D graphics-intensive applications are predicted to become widely available on a variety of portable mobile devices ranging from laptops to PDAs to mobile phones. Such 3D graphics coprocessors were originally...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Sep 2009

    Verifying External Interrupts of Embedded Microprocessor in SoC with On-Chip Bus

    The microprocessor verification challenge becomes higher in the On-Chip Bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. In this paper the authors propose an automatic method to verify the...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2011

    An Optimizing Compiler for Out-of-Order Parallel ESL Simulation Exploiting Instance Isolation

    Electronic System-Level (ESL) design relies on fast Discrete Event (DE) simulation for the validation of design models written in System-Level Description Languages (SLDLs). An advanced technique to speedup ESL validation is out-of-order parallel DE simulation which allows multiple threads to run early and in parallel on multi-core hosts. To avoid...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Mar 2011

    Online Capacity Identification of Multitier Websites Using Hardware Performance Counters

    Understanding server capacity is crucial to system capacity planning, configuration, and QoS-aware resource management. Conventional stress testing approaches measure server capacity offline in terms of application-level performance metrics like response time and throughput. They are limited in measurement accuracy and timeliness. In a multitier website, resource bottleneck often shifts between...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Dec 2006

    EQoS: Provisioning of Client-Perceived End-to-End QoS Guarantees in Web Servers

    It is important to guarantee client-perceived end-to-end Quality-of-Service (QoS) under heavy load conditions. Existing work focuses on network transfer time or server-side request processing time. In this paper, the authors propose a novel framework, eQoS, to monitor and control client-perceived response time in heavy loaded Web servers. The response time...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Jun 2011

    PERFUME: Power and Performance Guarantee with Fuzzy MIMO Control in Virtualized Servers

    It is important but challenging to assure the performance of multi-tier Internet applications with the power consumption cap of virtualized server clusters mainly due to system complexity of shared infrastructure and dynamic and bursty nature of workloads. This paper presents PERFUME, a system that simultaneously guarantees power and performance targets...

    Provided By Institute of Electrical & Electronic Engineers

  • White Papers // Sep 2010

    Autonomic Provisioning With Self-Adaptive Neural Fuzzy Control for End-to-End Delay Guarantee

    Autonomic server provisioning for performance assurance is a critical issue in data centers. It is important but challenging to guarantee an important performance metric, percentile-based end-to-end delay of requests flowing through a virtualized multi-tier server cluster. It is mainly due to dynamically varying workload and the lack of an accurate...

    Provided By Institute of Electrical & Electronic Engineers