Israel Institute of Technology

Displaying 1-40 of 56 results

  • White Papers // May 2014

    On the Channel Induced by Sneak-Path Errors in Memristor Arrays

    Memristors, also known as resistive RAMs, are very promising non-volatile media that can be packed in unprecedented density. However, the crossbar layout by which this high density is achieved entails major challenges arising from cell-to-cell interference. In particular, cell readout is affected by sneak paths, which are electric paths passing...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2014

    LDPC Codes for Partial-Erasure Channels in Multi-Level Memories

    In this paper, the authors develop a new channel model, which they name the Q-ary Partial Erasure Channel (QPEC). QPEC has a q-ary input, and its output is either one symbol or a set of M possible values. This channel mimics situations when current/voltage levels in measurement channels are only...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2014

    Codes for High Performance Write and Read Processes in Multi-Level NVMs

    Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multilevel cells, however, imposes higher read and write latencies limiting high speed applications. In this paper, the authors study the tradeoff between storage density and write/read performance using codes. The contributions are codes that...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2014

    Decentralized Electronic Mail

    E-mail is one of the most popular Internet applications. Unfortunately, the server-centric architecture of today's commercial solutions inherently limits availability, efficiency and scalability. The single point of failure as well as the increasing processing and storage stress on the server drives the 35 year old infrastructure to the limits of...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2014

    Asynchronous Bit-stream Compression (ABC)

    Asynchronous signaling is used for high speed data communication in large Systems-on-Chip (SoC). The bandwidth limitations of serial link dictate a need for real-time compression techniques. In this paper, the authors propose a new technique of Asynchronous Bit-stream Compression (ABC), based on Level Encoded Dual-Rail (LEDR) protocol. The ABC method...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2013

    Cryptanalysis of Iterated Even-Mansour Schemes with Two Keys

    The iterated Even-Mansour (EM) scheme is a generalization of the original 1-round construction proposed in 1991, and can use one key, two keys, or completely independent keys. In this paper, the authors methodically analyze the security of all the possible iterated Even-Mansour schemes with two n-bit keys and up to...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2013

    Adaptive Threshold Read Algorithms in Multi-level Non-Volatile Memories

    For an array of memory cells that are read by threshold measurements, the authors ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. They propose and study analytically and experimentally various adaptive read algorithms,...

    Provided By Israel Institute of Technology

  • White Papers // Jul 2013

    ViLoCoN - An Ultra-Lightweight Lossless VLSI Video Codec

    A novel lossless image and video codec termed ViLoCoN is presented. ViLoCoN stands for Video Lossless Compression for NoCs (i.e. Network-on-Chips) as it is highly applicable to reduce power consumption and bandwidth of on-chip and inter chip interconnect in modern multimedia SoCs. ViLoCoN's encoder/decoder uses fewer gates (71% and 84%)...

    Provided By Israel Institute of Technology

  • White Papers // May 2013

    Retired-Page Utilization in Write-Once Memory - A Coding Perspective

    In write-once memory (e.g., flash), a cell's level can only be raised, and erasure is only in bulk. The total number of erasures (endurance) is limited, and drops sharply with technology shrinkage and with cell-capacity increase. The normalized write capacity (ratio of total amount of data that can be written...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2013

    GESPAR: Efficient Phase Retrieval of Sparse Signals

    The authors consider the problem of One Dimensional (1D) phase retrieval, namely, recovery of a 1D signal from the magnitude of its Fourier transform. This problem is ill-posed since the Fourier phase information is lost. Therefore, prior information on the signal is needed in order to recover it. In this...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2012

    Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

    Hierarchical topologies are frequently proposed for large Network-on-Chips (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC delays of long links might reach dozens of clock cycles in advanced technology nodes, if delay reduction techniques (e.g. wire sizing and repeater insertion)...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2012

    Dynamic Traffic Distribution Among Hierarchy Levels in Hierarchical Networks-on-Chip (NoCs)

    As the number of modules grows, performance scalability of planar topology Network-on-Chips (NoCs) becomes limited due to the increasing hop-distances. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide better traffic hop distance and therefore are more adequate for large systems. However, the introduction...

    Provided By Israel Institute of Technology

  • White Papers // Nov 2012

    Memory Array Microarchitecture: Algorithmic Techniques for Density and Performance Enhancement

    Device shrinkage enables higher storage densities and lower power consumption per memory cell. Yet, there is a fly in the ointment. Decreasing device dimensions results in major data integrity issues, such as inter-cell interference, where the content of memory cell is affected by the content of its neighbors. The authors...

    Provided By Israel Institute of Technology

  • White Papers // Nov 2012

    Low-Complexity Two-Dimensional Data Encoding for Memory Inter-Cell Interference Reduction

    Inter-cell Coupling Interference (ICI) affects capacity, performance, reliability and endurance of semiconductor memories, particularly NAND Flash. Constrained coding of a row of cells has been proposed for ICI mitigation by forbidding data patterns that induce interference above a chosen threshold level. The authors expand the interference model to two dimensions,...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2012

    Probabilistic Performance of Write-Once Memory with Linear WOM Codes - Analysis and Insights

    The level of write-once memory cells (e.g., Flash) can only be raised individually. Bulk erasure is possible, but only a number of times (endurance) that decreases sharply with increasing cell capacity or cell-size reduction. A device's declared storage capacity and the total amount of information that can be written to...

    Provided By Israel Institute of Technology

  • White Papers // Aug 2012

    MRL - Memristor Ratioed Logic

    Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS...

    Provided By Israel Institute of Technology

  • White Papers // Jun 2012

    Evaluation of a Speech Bandwidth Extension Algorithm Based on Vocal Tract Shape Estimation

    In this paper, the authors evaluate a speech BandWidth Extension (BWE) algorithm which involves phonetic and speaker dependent estimation of the high-band part of the spectral envelope. The BWE algorithm extracts speech phoneme information by using a hidden Markov model. Speaker vocal tract shape information corresponding to the wideband signal...

    Provided By Israel Institute of Technology

  • White Papers // May 2012

    The Resource-as-a-Service (RaaS) Cloud

    Over the next few years, a new model of buying and selling cloud computing resources will evolve. Instead of providers exclusively selling server equivalent virtual machines for relatively long periods of time (as done in today's IaaS clouds), providers will increasingly sell individual resources (such as CPU, memory, and I/O...

    Provided By Israel Institute of Technology

  • White Papers // May 2012

    Persistent OSPF Attacks

    Open Shortest Path First (OSPF) is the most widely deployed interior gateway routing protocol on the internet. The authors present two new attacks on OSPF that expose design vulnerabilities in the protocol specification. These new attacks can affect routing advertisements of routers not controlled by the attacker while evading the...

    Provided By Israel Institute of Technology

  • White Papers // Mar 2012

    Sparsity Constrained Nonlinear Optimization: Optimality Conditions and Algorithms

    This paper treats the problem of minimizing a general continuously differentiable function subject to sparsity constraints. The authors present and analyze several different optimality criteria which are based on the notions of stationarity and coordinate-wise optimality. These conditions are then used to derive three numerical algorithms aimed at finding points...

    Provided By Israel Institute of Technology

  • White Papers // Mar 2012

    On Real-Time and Causal Secure Source Coding

    The authors investigate two source coding problems with secrecy constraints. In the first problem they consider real - time fully secure transmission of a memoryless source. They show that although classical variable - rate coding is not an option since the lengths of the codewords leak information on the source,...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2012

    Zero Meta-Data Prefetch Algorithms for Hierarchical Storage

    The authors propose a new scheme to prefetch data blocks from slow to fast storage in hierarchical storage. The advantage of the proposed scheme is that no meta-data is used to record past accesses, and selection is decided solely based on the blocks present in small request windows. This property...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2012

    ExPERT: Pareto-Efficient Task Replication on Grids and a Cloud

    Many scientists perform extensive computations by executing large Bags of similar Tasks (BoTs) in mixtures of computational environments, such as grids and clouds. Although the reliability and cost may vary considerably across these environments, no tool exists to assist scientists in the selection of environments that can both fulfill deadlines...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2012

    Perfectly Secure Encryption of Individual Sequences

    In analogy to the well - known notion of finite - state compressibility of individual sequences, due to Lempel and Ziv, the authors define a similar notion of "Finite - state encryptability" of an individual plain-text sequence, as the minimum asymptotic key rate that must be consumed by finite -...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2011

    Deconstructing Amazon EC2 Spot Instance Pricing

    Cloud providers possessing large quantities of spare capacity must either incentivize clients to purchase it or suffer losses. Amazon is the first cloud provider to address this challenge, by allowing clients to bid on spare capacity and by granting resources to bidders while their bids exceed a periodically changing spot...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2011

    Hybrid Digital/Analog Schemes for Secure Transmission with Side Information

    Recent results on source-channel coding for secure transmission show that separation holds in several cases under some less-noisy conditions. However, it has also been proved through a simple counterexample that pure analog schemes can be optimal and hence outperform digital ones. According to these observations and assuming matched bandwidth, the...

    Provided By Israel Institute of Technology

  • White Papers // Jun 2011

    Constrained Flash Memory Programming

    In NAND flash memory featuring Multi-Level Cells (MLC), the width of threshold voltage distributions about their nominal values affects the permissible number of levels and thus storage capacity. Unfortunately, inter-cell coupling causes a cell's charge to affect its neighbors' sensed threshold voltage, resulting in an apparent broadening of these distributions....

    Provided By Israel Institute of Technology

  • White Papers // May 2011

    Secure Lossy Source-Channel Wiretapping with Side Information at the Receiving Terminals

    This paper aims to highlight current trends on the market of corporate antivirus solutions. Brief overview of modern security threats that can destroy IT environment is provided as well as a typical structure and features of antivirus suits for corporate users presented on the market. The detailed analysis of new...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2011

    ExPERT: Pareto-Efficient Task Replication on Grids and Clouds

    Many scientists perform extensive computations by executing large Bags of similar Tasks (BoTs) in mixtures of computational environments, such as grids and clouds. Although the reliability and cost may vary considerably across these environments, no tool exists to assist scientists in the selection of environments that can both fulfill deadlines...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2011

    Error Correction Scheme for Constrained Inter-Cell Interference in Flash Memory

    As NAND Flash memory process technology scales below 32nm and the number of charge levels per cell exceeds four, cell threshold voltage distributions must be narrower in order to prevent errors resulting from distribution overlap. An obstacle to achieving narrow distributions is the Floating-Gate (FG) to floating-gate coupling. This coupling...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2011

    Tolerant Value Speculation in Coarse-Grain Streaming Computations

    Streaming applications are the subject of growing interest, as the need for fast access to data continues to grow. In this paper, the authors present the design requirements and implementation of coarse-grain value speculation in streaming applications. They explain how this technique can be useful in cases where serial parts...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

    A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by down-sizing of the gates. Such a design flow is interesting because design methods had been traditionally focused on performance; Hence, deeply rooted engineering practices...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    A Shared File System Abstraction for Heterogeneous Architectures

    The authors advocate the use of high-level OS abstractions in heterogeneous systems, such as CPU-GPU hybrids. They suggest the idea of an Inter-Device shared File System (IDFS) for such architectures. The file system provides a unified storage space for seamless data sharing among processors and accelerators via a standard well...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Precomputation Schemes for QoS Routing

    Precomputation-based methods have recently been proposed as an instrument to facilitate scalability, improve response time and reduce computation load on network elements. The key idea is to effectively reduce the time needed to handle an event by performing a certain amount of computations in advance, i.e., prior to the event's...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Low-Leakage Repeaters for NoC Interconnects

    Several low-leakage repeater circuits for Network-on-Chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed Staggered-VT (SVT) repeater is compared with novel Dual-vT Domino (DTD) repeaters and Sleep Repeaters (SR). These circuits are compared with standard Low-VT (LVT) repeaters in a 32-bit link. Up to 70%...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Nahalal: Memory Organization for Chip Multiprocessors

    This paper addresses cache organization in Chip MultiProcessor (CMPs). The authors introduce Nahalal, a novel Non-Uniform CAche (NUCA) topology that enables fast access to shared data for all processors, while preserving the vicinity of private data to each processor. Their characterization of memory accesses patterns in typical parallel programs shows...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Not All at Once! - A Generic Scheme for Estimating the Number of Affected Nodes While Avoiding Feedback Implosion

    The authors present a generic scheme for estimating the size of a group of nodes affected by the same event in a large-scale network, such as a grid, a sensor network or a wireless broadband access network, while receiving only a small number of feedback messages from this group. Using...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2010

    ABC - A New Framework for Block Ciphers

    The authors suggest a new framework for block ciphers named Advanced Block Cipher, or shortly ABC. ABC has additional non-secret parameters that ensure that each call to the underlying block cipher uses a different pseudorandom permutation. It therefore ensures that attacks that require more than one block encrypted under the...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2010

    RAPID: Reliable Probabilistic Dissemination in Wireless Ad-Hoc Networks

    Reliable broadcast is a basic service for many collaborative applications as it provides reliable dissemination of the same information to many recipients. In this paper, the authors propose a novel ReliAble ProbabIlistic Dissemination protocol, called RAPID, for mobile wireless ad-hoc networks that tolerates message omissions, node crashes, and selfish behavior....

    Provided By Israel Institute of Technology

  • White Papers // Nov 2010

    Content-Based Validation of Business Process Models

    In this paper, the authors present a methodology for content-based validation of business process models, focusing on existing organizational policies. This methodology goes beyond structural notation and pro-poses to automatically extract business logic from process repositories as a basis for content validation. Each process activity is encoded automatically as a...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    A Shared File System Abstraction for Heterogeneous Architectures

    The authors advocate the use of high-level OS abstractions in heterogeneous systems, such as CPU-GPU hybrids. They suggest the idea of an Inter-Device shared File System (IDFS) for such architectures. The file system provides a unified storage space for seamless data sharing among processors and accelerators via a standard well...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2010

    Reconfiguring Replicated Atomic Storage: A Tutorial

    The people live in a world of Internet services such as email, social networks, web searching, and more, which must store increasingly larger volumes of data. These services must run on cheap infrastructure, hence they must use distributed storage systems; and they have to provide reliability of data for long...

    Provided By Israel Institute of Technology

  • White Papers // May 2009

    Distributed Clustering for Robust Aggregation in Large Networks

    In years to come, the authors can expect to see sensor networks with thousands of light-weight nodes monitoring conditions like seismic activity or temperature. In addition, large-scale networked services are now being increasingly deployed in computation clouds and Internet-based overlay networks. They present a scalable protocol for robust data aggregation...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2014

    Decentralized Electronic Mail

    E-mail is one of the most popular Internet applications. Unfortunately, the server-centric architecture of today's commercial solutions inherently limits availability, efficiency and scalability. The single point of failure as well as the increasing processing and storage stress on the server drives the 35 year old infrastructure to the limits of...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

    A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by down-sizing of the gates. Such a design flow is interesting because design methods had been traditionally focused on performance; Hence, deeply rooted engineering practices...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2010

    The Complexity of VLSI Power-Delay Optimization by Interconnect Resizing

    The lithography used for 32 nanometers and smaller VLSI process technologies restricts the interconnect widths and spaces to a very small set of admissible values. Until recently the sizes of interconnects were allowed to change continuously and the implied power delay optimal tradeoff could be formulated as a convex programming...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2011

    Tolerant Value Speculation in Coarse-Grain Streaming Computations

    Streaming applications are the subject of growing interest, as the need for fast access to data continues to grow. In this paper, the authors present the design requirements and implementation of coarse-grain value speculation in streaming applications. They explain how this technique can be useful in cases where serial parts...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2014

    Asynchronous Bit-stream Compression (ABC)

    Asynchronous signaling is used for high speed data communication in large Systems-on-Chip (SoC). The bandwidth limitations of serial link dictate a need for real-time compression techniques. In this paper, the authors propose a new technique of Asynchronous Bit-stream Compression (ABC), based on Level Encoded Dual-Rail (LEDR) protocol. The ABC method...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2012

    Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

    Hierarchical topologies are frequently proposed for large Network-on-Chips (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC delays of long links might reach dozens of clock cycles in advanced technology nodes, if delay reduction techniques (e.g. wire sizing and repeater insertion)...

    Provided By Israel Institute of Technology

  • White Papers // Jul 2013

    ViLoCoN - An Ultra-Lightweight Lossless VLSI Video Codec

    A novel lossless image and video codec termed ViLoCoN is presented. ViLoCoN stands for Video Lossless Compression for NoCs (i.e. Network-on-Chips) as it is highly applicable to reduce power consumption and bandwidth of on-chip and inter chip interconnect in modern multimedia SoCs. ViLoCoN's encoder/decoder uses fewer gates (71% and 84%)...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2012

    Dynamic Traffic Distribution Among Hierarchy Levels in Hierarchical Networks-on-Chip (NoCs)

    As the number of modules grows, performance scalability of planar topology Network-on-Chips (NoCs) becomes limited due to the increasing hop-distances. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide better traffic hop distance and therefore are more adequate for large systems. However, the introduction...

    Provided By Israel Institute of Technology

  • White Papers // Aug 2012

    MRL - Memristor Ratioed Logic

    Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2010

    Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors

    In this paper, the authors evaluate new techniques to improve performance, fairness and jitter of workloads consisting of multiple multithreaded applications running on Chip Multi-Processors (CMP). Current thread assignment techniques which are tailored for single-thread applications result in sub-optimal usage of the multiprocessor resources, unfairness between applications and jitter in...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2008

    Power Saving in CMOS Processors by Optimal Wire Spacing

    Interconnect power is a significant part of dynamic power dissipation in microprocessors. Cross-capacitance between adjacent wires is a major contributor to this power consumption, and it can be reduced by post-processing of the layout for optimal allocation of spaces between wires. Necessary and sufficient conditions for the existence of optimal...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2007

    An Effective Technique for Simultaneous Interconnect Channel Delay and Noise Reduction in Nanometer VLSI Design

    Capacitive coupling is the primary source of noise in nanometer technology digital CMOS VLSI circuits. It becomes worse with technology scaling. The interconnect capacitive crosstalk noise can be characterized by two parameters: peak noise voltage, and delay uncertainty. Delay uncertainty optimization can be seen as a subset of interconnect delay...

    Provided By Israel Institute of Technology

  • White Papers // May 2014

    On the Channel Induced by Sneak-Path Errors in Memristor Arrays

    Memristors, also known as resistive RAMs, are very promising non-volatile media that can be packed in unprecedented density. However, the crossbar layout by which this high density is achieved entails major challenges arising from cell-to-cell interference. In particular, cell readout is affected by sneak paths, which are electric paths passing...

    Provided By Israel Institute of Technology

  • White Papers // May 2013

    Retired-Page Utilization in Write-Once Memory - A Coding Perspective

    In write-once memory (e.g., flash), a cell's level can only be raised, and erasure is only in bulk. The total number of erasures (endurance) is limited, and drops sharply with technology shrinkage and with cell-capacity increase. The normalized write capacity (ratio of total amount of data that can be written...

    Provided By Israel Institute of Technology

  • White Papers // Nov 2012

    Memory Array Microarchitecture: Algorithmic Techniques for Density and Performance Enhancement

    Device shrinkage enables higher storage densities and lower power consumption per memory cell. Yet, there is a fly in the ointment. Decreasing device dimensions results in major data integrity issues, such as inter-cell interference, where the content of memory cell is affected by the content of its neighbors. The authors...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2011

    Error Correction Scheme for Constrained Inter-Cell Interference in Flash Memory

    As NAND Flash memory process technology scales below 32nm and the number of charge levels per cell exceeds four, cell threshold voltage distributions must be narrower in order to prevent errors resulting from distribution overlap. An obstacle to achieving narrow distributions is the Floating-Gate (FG) to floating-gate coupling. This coupling...

    Provided By Israel Institute of Technology

  • White Papers // Nov 2012

    Low-Complexity Two-Dimensional Data Encoding for Memory Inter-Cell Interference Reduction

    Inter-cell Coupling Interference (ICI) affects capacity, performance, reliability and endurance of semiconductor memories, particularly NAND Flash. Constrained coding of a row of cells has been proposed for ICI mitigation by forbidding data patterns that induce interference above a chosen threshold level. The authors expand the interference model to two dimensions,...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2010

    Distributed Data Classification in Sensor Networks

    Low overhead analysis of large distributed data sets is necessary for current data centers and for future sensor networks. In such systems, each node holds some data value, e.g., a local sensor read, and a concise picture of the global system state needs to be obtained. To this end, the...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2012

    Probabilistic Performance of Write-Once Memory with Linear WOM Codes - Analysis and Insights

    The level of write-once memory cells (e.g., Flash) can only be raised individually. Bulk erasure is possible, but only a number of times (endurance) that decreases sharply with increasing cell capacity or cell-size reduction. A device's declared storage capacity and the total amount of information that can be written to...

    Provided By Israel Institute of Technology

  • White Papers // Jun 2011

    Constrained Flash Memory Programming

    In NAND flash memory featuring Multi-Level Cells (MLC), the width of threshold voltage distributions about their nominal values affects the permissible number of levels and thus storage capacity. Unfortunately, inter-cell coupling causes a cell's charge to affect its neighbors' sensed threshold voltage, resulting in an apparent broadening of these distributions....

    Provided By Israel Institute of Technology

  • White Papers // Sep 2010

    Integrating De-Duplication and Write for Increased Performance and Endurance of Solid-State Drives

    Modern NAND Flash-based Solid-State Drives (SSD) presents low latency, high throughput, low power consumption and solid-state reliability improvements comparing to traditional magnetic-disk based Hard Disk Drives (HDD). However, due to NAND Flash memory cell characteristics, update-in-place is impossible. Instead, the Flash software layer allocates new storage space whenever data is...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2011

    ExPERT: Pareto-Efficient Task Replication on Grids and Clouds

    Many scientists perform extensive computations by executing large Bags of similar Tasks (BoTs) in mixtures of computational environments, such as grids and clouds. Although the reliability and cost may vary considerably across these environments, no tool exists to assist scientists in the selection of environments that can both fulfill deadlines...

    Provided By Israel Institute of Technology

  • White Papers // Feb 2012

    Zero Meta-Data Prefetch Algorithms for Hierarchical Storage

    The authors propose a new scheme to prefetch data blocks from slow to fast storage in hierarchical storage. The advantage of the proposed scheme is that no meta-data is used to record past accesses, and selection is decided solely based on the blocks present in small request windows. This property...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2014

    Codes for High Performance Write and Read Processes in Multi-Level NVMs

    Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multilevel cells, however, imposes higher read and write latencies limiting high speed applications. In this paper, the authors study the tradeoff between storage density and write/read performance using codes. The contributions are codes that...

    Provided By Israel Institute of Technology

  • White Papers // Apr 2014

    LDPC Codes for Partial-Erasure Channels in Multi-Level Memories

    In this paper, the authors develop a new channel model, which they name the Q-ary Partial Erasure Channel (QPEC). QPEC has a q-ary input, and its output is either one symbol or a set of M possible values. This channel mimics situations when current/voltage levels in measurement channels are only...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2013

    Adaptive Threshold Read Algorithms in Multi-level Non-Volatile Memories

    For an array of memory cells that are read by threshold measurements, the authors ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. They propose and study analytically and experimentally various adaptive read algorithms,...

    Provided By Israel Institute of Technology

  • White Papers // May 2009

    The Capacity Allocation Paradox

    The Capacity Allocation Paradox (CAP) destabilizes a stable small-buffer network when a link capacity is increased. CAP is demonstrated in a basic 2x1 network topology. The authors show that it applies to fluid, wormhole and packet-switched networks, and prove that it applies to various scheduling algorithms such as fixed-priority, round-robin...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Low-Leakage Repeaters for NoC Interconnects

    Several low-leakage repeater circuits for Network-on-Chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed Staggered-VT (SVT) repeater is compared with novel Dual-vT Domino (DTD) repeaters and Sleep Repeaters (SR). These circuits are compared with standard Low-VT (LVT) repeaters in a 32-bit link. Up to 70%...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Nahalal: Memory Organization for Chip Multiprocessors

    This paper addresses cache organization in Chip MultiProcessor (CMPs). The authors introduce Nahalal, a novel Non-Uniform CAche (NUCA) topology that enables fast access to shared data for all processors, while preserving the vicinity of private data to each processor. Their characterization of memory accesses patterns in typical parallel programs shows...

    Provided By Israel Institute of Technology

  • White Papers // Oct 2009

    Networking Mobile Devices and Computers in an Intelligent Home

    This paper presents the prototype of a universal model for implementing the smart home. In this model, computers and various digital devices form a single network that operates at a high level of intelligence to provide and manage common services. The universal model includes a standard framework that will enable...

    Provided By Israel Institute of Technology

  • White Papers // Dec 2010

    RAPID: Reliable Probabilistic Dissemination in Wireless Ad-Hoc Networks

    Reliable broadcast is a basic service for many collaborative applications as it provides reliable dissemination of the same information to many recipients. In this paper, the authors propose a novel ReliAble ProbabIlistic Dissemination protocol, called RAPID, for mobile wireless ad-hoc networks that tolerates message omissions, node crashes, and selfish behavior....

    Provided By Israel Institute of Technology

  • White Papers // Jan 2011

    Not All at Once! - A Generic Scheme for Estimating the Number of Affected Nodes While Avoiding Feedback Implosion

    The authors present a generic scheme for estimating the size of a group of nodes affected by the same event in a large-scale network, such as a grid, a sensor network or a wireless broadband access network, while receiving only a small number of feedback messages from this group. Using...

    Provided By Israel Institute of Technology

  • White Papers // May 2011

    Secure Lossy Source-Channel Wiretapping with Side Information at the Receiving Terminals

    This paper aims to highlight current trends on the market of corporate antivirus solutions. Brief overview of modern security threats that can destroy IT environment is provided as well as a typical structure and features of antivirus suits for corporate users presented on the market. The detailed analysis of new...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2011

    Hybrid Digital/Analog Schemes for Secure Transmission with Side Information

    Recent results on source-channel coding for secure transmission show that separation holds in several cases under some less-noisy conditions. However, it has also been proved through a simple counterexample that pure analog schemes can be optimal and hence outperform digital ones. According to these observations and assuming matched bandwidth, the...

    Provided By Israel Institute of Technology

  • White Papers // Sep 2010

    Achievable Rates for the Broadcast Channel with States Known at the Transmitter

    Broadcast channels have been studied intensively, due to their role in communication networks. The basic definitions of this model, with a survey of important contributions, can be found in. In this paper, the authors study coding for the general broadcast channel, controlled by random parameters, where the parameters are provided...

    Provided By Israel Institute of Technology

  • White Papers // Nov 2010

    Content-Based Validation of Business Process Models

    In this paper, the authors present a methodology for content-based validation of business process models, focusing on existing organizational policies. This methodology goes beyond structural notation and pro-poses to automatically extract business logic from process repositories as a basis for content validation. Each process activity is encoded automatically as a...

    Provided By Israel Institute of Technology

  • White Papers // Jan 2013

    GESPAR: Efficient Phase Retrieval of Sparse Signals

    The authors consider the problem of One Dimensional (1D) phase retrieval, namely, recovery of a 1D signal from the magnitude of its Fourier transform. This problem is ill-posed since the Fourier phase information is lost. Therefore, prior information on the signal is needed in order to recover it. In this...

    Provided By Israel Institute of Technology