Kyushu University

Displaying 1-40 of 71 results

  • White Papers // Jan 2014

    Dependability, Power, and Performance Trade-off on a Multicore Processor

    As deep submicron technologies are advanced, the authors face new challenges, such as power consumption and soft errors. A na

    Provided By Kyushu University

  • White Papers // Nov 2012

    MD: Minimal Path-Based Fault-Tolerant Routing in On-Chip Networks

    The communication requirements of many-core embedded systems are convened by the emerging Network-on-Chip (NoC) paradigm. As on-chip communication reliability is a crucial factor in many-core systems, the NoC paradigm should address the reliability issues. Using fault-tolerant routing algorithms to reroute packets around faulty regions will increase the packet latency and...

    Provided By Kyushu University

  • White Papers // Oct 2012

    Detecting Information Leakage via a HTTP Request Based on the Edit Distance

    Recently, the people often face the problem of information leakage. They propose a leakage detection system which is independent of a database. This system focuses on the leakage caused by human action and malware. In an existing research, researchers calculate an edit distance between the last HTTP request and the...

    Provided By Kyushu University

  • White Papers // Sep 2012

    Power and Performance Analysis of GPU-Accelerated Systems

    Graphics Processing Units (GPUs) provide significant improvements in performance and performance-per-watt as compared to traditional multicore CPUs. This energy-efficiency of GPUs has facilitated the use of GPUs in many application domains. Albeit energy efficient GPUs consume non-trivial power independently of CPUs. Therefore, the authors need to analyze the power and...

    Provided By Kyushu University

  • White Papers // Aug 2012

    Public Key Replacement and Universal Forgery of SCLS Scheme

    Certificateless cryptography eliminates the need of certificates in the PKI and solves the inherent key escrow problem in the ID-based cryptography. Recently, Du and Wen proposed a Short Certificateless Signature Scheme (SCLS) without MapToPoint hash function, and the signature size is short enough with only half of the DSA signature....

    Provided By Kyushu University

  • White Papers // May 2012

    Public-Key Cryptography From New Multivariate Quadratic Assumptions

    In this paper, the authors study a new Multivariate Quadratic (MQ) assumption that can be used to construct public-key encryption schemes. In particular, they research in the following two directions: they establish a precise asymptotic formulation of a family of hard MQ problems, and provide empirical evidence to confirm the...

    Provided By Kyushu University

  • White Papers // Apr 2012

    Security Analysis of Offline E-Cash Systems with Malicious Insider

    When the electronic cash systems are built, the main focus of the design is usually on preventing customers' malicious actions. However, since authorities such as banks and certificate authorities may have important secret data of customers, the insiders in the potentially untrusted authorities can become threats to electronic cash systems....

    Provided By Kyushu University

  • White Papers // Dec 2011

    A Thermal-Aware Mapping Algorithm for Reducing Peak Temperature of an Accelerator Deployed in a 3D Stack

    Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has...

    Provided By Kyushu University

  • White Papers // Oct 2011

    Performance Evaluations of Finite Difference Applications Realized on a Single Flux Quantum Circuits-Based Reconfigurable Accelerator

    Hardware accelerators integrating to general purpose processors are increasingly employed to achieve lower power consumption and higher processing speed, however, energy consumption of high performance accelerators has become a great issue on large scale parallel computer system. The authors have investigated the applicability of Single-Flux-Quantum (SFQ) circuits as a part...

    Provided By Kyushu University

  • White Papers // Sep 2011

    Enhancing SVO Logic for Mobile IPv6 Security Protocols

    In order to protect Mobile Internet Protocol Version 6 (MIPv6), considerable researches have been made, consequently followed by various security protocols, which are based on public key cryptography. Especially, depending on a proper address based public key method, these protocols use each node's address as a public key certificate to...

    Provided By Kyushu University

  • White Papers // Aug 2011

    A Training Based Transmission Period Setting Protocol

    The authors have proposed Intermittent Periodic Transmission (IPT forwarding) as an efficient packet relay method for wireless backhaul. In IPT forwarding, a source node sends packets to a destination node with a certain time interval (IPT duration) so that signal interference between relay nodes that send packets simultaneously are reduced...

    Provided By Kyushu University

  • White Papers // Jun 2011

    Energy Efficient Scheduling for Multithreaded Programs on General-Purpose Processors

    In this paper, the authors investigates the effectiveness of Time Aggregation Scheduler (TAS) for commodity platforms from the view point of energy saving. TAS can aggregate the execution of runnable sibling threads, and decrease the number of internal events that have negative impact on energy consumption in executing multithreaded applications....

    Provided By Kyushu University

  • White Papers // Jun 2011

    Hardware and Software Requirements for Implementing a High-Performance Superconductivity Circuits-Based Accelerator

    Single-Flux Quantum based Large-Scale Data-Path processor (SFQ-LSRDP) is a reconfigurable computing system which is implemented by means of superconductivity circuits. SFQ-LSRDP has a capability of accelerating Data Flow Graphs (DFGs) extracted from scientific applications. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints...

    Provided By Kyushu University

  • White Papers // May 2011

    IEEE 802.11n Based Wireless Backhaul Enabled by Dual Channel IPT (DCH-IPT) Forwarding

    Wireless backhaul has received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high throughput with a minimum delay network is highly appreciated to sustain the increasing proliferation in multimedia transmissions. In...

    Provided By Kyushu University

  • White Papers // Mar 2011

    Routing Architecture and Algorithms for a Superconductivity Circuits-Based Computing Hardware

    Dedicated tools for placing and routing data flow graphs extracted from computation-intensive applications are basic requirements for developing applications on a Large-Scale Reconfigurable Data-path Processor (LSRDP) implemented by superconductivity circuits. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints and conditions from the...

    Provided By Kyushu University

  • White Papers // Dec 2010

    Custom Instructions with Multiple Exits: Generation and Execution

    In this paper, the authors propose an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. A reconfigurable functional unit is utilized to support this feature. The proposed reconfigurable functional unit is based on a matrix of functional units which is multi-cycle with the capability of...

    Provided By Kyushu University

  • White Papers // Oct 2010

    Compiler Assisted Energy Reduction Techniques for Embedded Multimedia Processors

    Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. In this paper, the authors present their recent research activities and results on characterizing and reducing the energy consumption in embedded systems. A technique for characterizing the energy consumption of embedded processors during...

    Provided By Kyushu University

  • White Papers // Sep 2010

    A Replacement Strategy for Canary Flip-Flops

    The deep submicron semiconductor technologies increase parameter variations. The increase in parameter variations requires excessive design margin that has serious impact on performance and power consumption. In order to eliminate the excessive design margin, the authors are investigating canary Flip-Flop (FF). Canary FF requires additional circuits consisting of an FF...

    Provided By Kyushu University

  • White Papers // Jun 2010

    Reducing Preprocessing Overhead Times in a Reconfigurable Accelerator of Finite Difference Applications

    Hardware accelerators integrating to General Purpose Processors (GPPs) are increasingly employed to achieve lower power consumption and higher processing speed. However due to impact of memory-wall problem, this kind of acceleration does not always achieve a demanded performance. To resolve this issue, a Large-Scale Reconfigurable Data-Path (LSRDP) has been proposed...

    Provided By Kyushu University

  • White Papers // Apr 2010

    An Implementation of Energy Efficient Multi-Performance Processor for Real-Time Applications

    Dynamic Voltage and Frequency Scaling (DVFS) is one of the most popular approaches for reducing the energy consumption of microprocessors, which dynamically changes the supply voltage to the lowest value for saving the dynamic power consumption while it ensures a correct operation of the microprocessors. Multi-performance processor reduces the energy...

    Provided By Kyushu University

  • White Papers // Apr 2010

    A Secured Smart Card Using a Pseudorandom Affine Transformation Based Cipher and a Secured LIRKES

    The RKES (Remotely Keyed Encryption Schemes) are greatly useful in solving the vital problem of how to do bulk encryption/ decryption for high-bandwidth applications (Like multimedia and video encryption) in a way that takes advantage of both the superior power of the host and the superior security of the smart...

    Provided By Kyushu University

  • White Papers // Apr 2010

    A Novel Luby-Rackoff Based Cipher in a New Feistel-Network Based LPRKES for Smart Cards

    The RKES (Remotely Keyed Encryption Schemes) are greatly useful in solving the vital problem of how to do bulk encryption and decryption for high-bandwidth applications (like multimedia and video encryption) in a way that takes advantage of both the superior power of the host and the superior security of the...

    Provided By Kyushu University

  • White Papers // Mar 2010

    An Efficient Wireless Backhaul Utilizing MIMO Transmission and IPT Forwarding

    Wireless backhaul has been received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high performance network, high throughput, low average delay and low packet loss rate, is highly appreciated to sustain...

    Provided By Kyushu University

  • White Papers // Jan 2010

    Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits

    Since the clock power consumption in today's processors is considerably large, reducing the clock power consumption contributes to the reduction of the total power consumption in the processors. Recently, a gated flip-flop is proposed for reducing the clock power consumption of flip-flop circuits. The gated flip-flop employs a clock-gating circuit...

    Provided By Kyushu University

  • White Papers // Jan 2010

    Signal Probability Control for Relieving NBTI in SRAM Cells

    Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact...

    Provided By Kyushu University

  • White Papers // Dec 2009

    Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator

    As a solution to gain high performance computation, a Large-Scale Reconfigurable Data-Path (LSRDP) processor is introduced in this paper. LSRDP is implemented by virtue of single-flux quantum circuits and integrated to a general purpose processor to accelerate the execution of Data Flow Graphs (DFGs) extracted from scientific applications. Design procedure...

    Provided By Kyushu University

  • White Papers // Oct 2009

    Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units

    In this paper, the authors propose and evaluate their platform to accelerate applications using custom instruction set extensions. They use a Dynamically Reconfigurable Functional Unit (DRFU) to execute the application specific custom instructions generated by their compiler framework. They explore two architectures with different computational granularities for the DRFU (Look-Up...

    Provided By Kyushu University

  • White Papers // Sep 2009

    Optimal Stack Frame Placement and Transfer for Energy Reduction Targeting Embedded Processors with Scratch-Pad Memories

    Memory accesses are a major cause of energy consumption for embedded systems and the stack is a frequent target for data accesses. In this paper, the authors present a fully software technique which aims at reducing the energy consumption related to the stack by allocating and transferring frames or part...

    Provided By Kyushu University

  • White Papers // Sep 2009

    Real-Time Power Management for a Multi-Performance Processor

    In this paper, the authors present an energy efficient embedded processor which can be used as a design alternative for the Dynamic Voltage Scaling (DVS) processors in embedded real-time system design. The processor consists of multiple same-ISA PE (Processing Element) cores and a selective set-associative cache memory. The PE-cores differ...

    Provided By Kyushu University

  • White Papers // Aug 2009

    A Power-Aware Post-Processing Under Depth Constraint for LUT-Based FPGA Technology Mapping

    It is difficult for LookUp-Table (LUT)-based Field Programmable Gate Array (FPGA) technology mapping to generate a power-minimal K-input LUT network with minimum depth at one time because a problem for power-minimization was shown to be NP-hard. A problem for area-minimization is also NP-hard, and area-aware algorithms recover area after generating...

    Provided By Kyushu University

  • White Papers // Jul 2009

    Multi-Operand Adder Synthesis on FPGAs Using Generalized Parallel Counters

    Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carry propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters...

    Provided By Kyushu University

  • White Papers // Jul 2009

    Performance Balancing: Software-Based On-Chip Memory Management for Effective CMP Executions

    In this paper, the authors propose the concept of performance balancing, and report its performance impact on a Chip Multi-Processor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does...

    Provided By Kyushu University

  • White Papers // May 2009

    An Accelerator Based on Single-Flex Quantum Circuits for a High-Performance Reconfigurable Computer

    A Large-Scale Reconfigurable Data-Path (LSRDP) processor based on single-flux quantum circuits has been proposed to overcome the barriers originating from the CMOS technology. LSRDP is integrated to a General Purpose Processor (GPP) in a high-performance computing system to accelerate the execution of data flow graphs extracted from scientific applications. The...

    Provided By Kyushu University

  • White Papers // May 2009

    Optimizing the Architecture of SFQ-RDP (Single Flux Quantum-Reconfigurable Datapath)

    For providing high computational power to individual researchers in various scientific areas a desk-side tera-flop scale computer has been introduced which consists of a CMOS general purpose processor, a memory and a Single-Flux Quantum (SFQ)- based Large-Scale Reconfigurable Data-Path processor (SFQ-LSRDP) as an accelerator. A Large-Scale Reconfigurable Data-Path (LSRDP) processor...

    Provided By Kyushu University

  • White Papers // Apr 2009

    Uncriticality-Directed Scheduling for Tackling Variation and Power Challenges

    The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability. Increasing the supply voltage to reduce the delay should not be a solution, since it increases power consumption, which is another serious problem in microprocessor designs....

    Provided By Kyushu University

  • White Papers // Jan 2009

    Empirical Performance Models for Java Workloads

    Java is widely deployed on a variety of processor architectures. Consequently, an understanding of microarchitecture level Java performance is critical to optimize current systems and to aid design and development of future processor architectures for Java. Although this is facilitated by a rich set of processor performance counters featured on...

    Provided By Kyushu University

  • White Papers // Jan 2009

    Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories

    In this paper, the authors propose a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Their approach exploits a non-cacheable memory region for an effective use of a cache memory...

    Provided By Kyushu University

  • White Papers // Sep 2008

    A Single Cycle Accessible Two-Level Cache Architecture for Reducing the Energy Consumption of Embedded Systems

    Employing a small L0-cache between an MPU core and an L1-cache is one of the most promising approaches for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a...

    Provided By Kyushu University

  • White Papers // Sep 2008

    Performance Evaluation of a Reconfigurable Instruction Set Processor

    Reconfigurable Instruction Set Processors (RISPs) introduce an effective approach for implementing embedded systems similar to Application-Specific Instruction set Processors (ASIPs) and extensible processors. Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. A combined analytical and simulation-based model is proposed and validated for performance evaluation...

    Provided By Kyushu University

  • White Papers // Sep 2008

    A Sampling Microarchitecture Simulator for Java Workloads

    Java is widely used across a variety of hardware platforms ranging from embedded systems and desktop computers to high end enterprise servers. Designing and optimizing systems for Java execution across different system architectures requires an understanding of program execution characteristics and the effect of system parameters on different aspects of...

    Provided By Kyushu University

  • White Papers // Sep 2012

    Power and Performance Analysis of GPU-Accelerated Systems

    Graphics Processing Units (GPUs) provide significant improvements in performance and performance-per-watt as compared to traditional multicore CPUs. This energy-efficiency of GPUs has facilitated the use of GPUs in many application domains. Albeit energy efficient GPUs consume non-trivial power independently of CPUs. Therefore, the authors need to analyze the power and...

    Provided By Kyushu University

  • White Papers // May 2012

    Public-Key Cryptography From New Multivariate Quadratic Assumptions

    In this paper, the authors study a new Multivariate Quadratic (MQ) assumption that can be used to construct public-key encryption schemes. In particular, they research in the following two directions: they establish a precise asymptotic formulation of a family of hard MQ problems, and provide empirical evidence to confirm the...

    Provided By Kyushu University

  • White Papers // Apr 2012

    Security Analysis of Offline E-Cash Systems with Malicious Insider

    When the electronic cash systems are built, the main focus of the design is usually on preventing customers' malicious actions. However, since authorities such as banks and certificate authorities may have important secret data of customers, the insiders in the potentially untrusted authorities can become threats to electronic cash systems....

    Provided By Kyushu University

  • White Papers // Oct 2012

    Detecting Information Leakage via a HTTP Request Based on the Edit Distance

    Recently, the people often face the problem of information leakage. They propose a leakage detection system which is independent of a database. This system focuses on the leakage caused by human action and malware. In an existing research, researchers calculate an edit distance between the last HTTP request and the...

    Provided By Kyushu University

  • White Papers // Apr 2010

    A Secured Smart Card Using a Pseudorandom Affine Transformation Based Cipher and a Secured LIRKES

    The RKES (Remotely Keyed Encryption Schemes) are greatly useful in solving the vital problem of how to do bulk encryption/ decryption for high-bandwidth applications (Like multimedia and video encryption) in a way that takes advantage of both the superior power of the host and the superior security of the smart...

    Provided By Kyushu University

  • White Papers // Apr 2010

    A Novel Luby-Rackoff Based Cipher in a New Feistel-Network Based LPRKES for Smart Cards

    The RKES (Remotely Keyed Encryption Schemes) are greatly useful in solving the vital problem of how to do bulk encryption and decryption for high-bandwidth applications (like multimedia and video encryption) in a way that takes advantage of both the superior power of the host and the superior security of the...

    Provided By Kyushu University

  • White Papers // May 2011

    IEEE 802.11n Based Wireless Backhaul Enabled by Dual Channel IPT (DCH-IPT) Forwarding

    Wireless backhaul has received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high throughput with a minimum delay network is highly appreciated to sustain the increasing proliferation in multimedia transmissions. In...

    Provided By Kyushu University

  • White Papers // Mar 2010

    An Efficient Wireless Backhaul Utilizing MIMO Transmission and IPT Forwarding

    Wireless backhaul has been received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high performance network, high throughput, low average delay and low packet loss rate, is highly appreciated to sustain...

    Provided By Kyushu University

  • White Papers // Sep 2011

    Enhancing SVO Logic for Mobile IPv6 Security Protocols

    In order to protect Mobile Internet Protocol Version 6 (MIPv6), considerable researches have been made, consequently followed by various security protocols, which are based on public key cryptography. Especially, depending on a proper address based public key method, these protocols use each node's address as a public key certificate to...

    Provided By Kyushu University

  • White Papers // Aug 2011

    A Training Based Transmission Period Setting Protocol

    The authors have proposed Intermittent Periodic Transmission (IPT forwarding) as an efficient packet relay method for wireless backhaul. In IPT forwarding, a source node sends packets to a destination node with a certain time interval (IPT duration) so that signal interference between relay nodes that send packets simultaneously are reduced...

    Provided By Kyushu University

  • White Papers // Aug 2012

    Public Key Replacement and Universal Forgery of SCLS Scheme

    Certificateless cryptography eliminates the need of certificates in the PKI and solves the inherent key escrow problem in the ID-based cryptography. Recently, Du and Wen proposed a Short Certificateless Signature Scheme (SCLS) without MapToPoint hash function, and the signature size is short enough with only half of the DSA signature....

    Provided By Kyushu University

  • White Papers // Jun 2011

    Energy Efficient Scheduling for Multithreaded Programs on General-Purpose Processors

    In this paper, the authors investigates the effectiveness of Time Aggregation Scheduler (TAS) for commodity platforms from the view point of energy saving. TAS can aggregate the execution of runnable sibling threads, and decrease the number of internal events that have negative impact on energy consumption in executing multithreaded applications....

    Provided By Kyushu University

  • White Papers // Jul 2009

    Performance Balancing: Software-Based On-Chip Memory Management for Effective CMP Executions

    In this paper, the authors propose the concept of performance balancing, and report its performance impact on a Chip Multi-Processor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does...

    Provided By Kyushu University

  • White Papers // Aug 2007

    System-Level Techniques for Estimating and Reducing Energy Consumption in Real-Time Embedded Systems

    Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The authors present their recent research activities and results on estimating and reducing dynamic and static energy under real-time constraints in embedded systems. This paper includes techniques and tools for estimating instantaneous energy...

    Provided By Kyushu University

  • White Papers // Oct 2007

    Taking Advantage of Within-Die Delay-Variation to Reduce Cache Leakage Power Using Additional Cache-Ways

    Leakage power, especially in cache memories, is dominating total power consumption of processor-based embedded systems. By choosing a higher threshold voltage, SRAM leakage can be exponentially reduced in return for lower speed. Since SRAM cells in the same cache have different delays in nanometer technologies due to within-die process variation,...

    Provided By Kyushu University

  • White Papers // Aug 2007

    Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs

    Extracting frequently executed portions of the application and executing their corresponding Data Flow Graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs)...

    Provided By Kyushu University

  • White Papers // Apr 2010

    An Implementation of Energy Efficient Multi-Performance Processor for Real-Time Applications

    Dynamic Voltage and Frequency Scaling (DVFS) is one of the most popular approaches for reducing the energy consumption of microprocessors, which dynamically changes the supply voltage to the lowest value for saving the dynamic power consumption while it ensures a correct operation of the microprocessors. Multi-performance processor reduces the energy...

    Provided By Kyushu University

  • White Papers // Jun 2010

    Reducing Preprocessing Overhead Times in a Reconfigurable Accelerator of Finite Difference Applications

    Hardware accelerators integrating to General Purpose Processors (GPPs) are increasingly employed to achieve lower power consumption and higher processing speed. However due to impact of memory-wall problem, this kind of acceleration does not always achieve a demanded performance. To resolve this issue, a Large-Scale Reconfigurable Data-Path (LSRDP) has been proposed...

    Provided By Kyushu University

  • White Papers // Apr 2009

    Uncriticality-Directed Scheduling for Tackling Variation and Power Challenges

    The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability. Increasing the supply voltage to reduce the delay should not be a solution, since it increases power consumption, which is another serious problem in microprocessor designs....

    Provided By Kyushu University

  • White Papers // Aug 2009

    A Power-Aware Post-Processing Under Depth Constraint for LUT-Based FPGA Technology Mapping

    It is difficult for LookUp-Table (LUT)-based Field Programmable Gate Array (FPGA) technology mapping to generate a power-minimal K-input LUT network with minimum depth at one time because a problem for power-minimization was shown to be NP-hard. A problem for area-minimization is also NP-hard, and area-aware algorithms recover area after generating...

    Provided By Kyushu University

  • White Papers // Oct 2009

    Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units

    In this paper, the authors propose and evaluate their platform to accelerate applications using custom instruction set extensions. They use a Dynamically Reconfigurable Functional Unit (DRFU) to execute the application specific custom instructions generated by their compiler framework. They explore two architectures with different computational granularities for the DRFU (Look-Up...

    Provided By Kyushu University

  • White Papers // Jan 2014

    Dependability, Power, and Performance Trade-off on a Multicore Processor

    As deep submicron technologies are advanced, the authors face new challenges, such as power consumption and soft errors. A na

    Provided By Kyushu University

  • White Papers // Sep 2008

    A Sampling Microarchitecture Simulator for Java Workloads

    Java is widely used across a variety of hardware platforms ranging from embedded systems and desktop computers to high end enterprise servers. Designing and optimizing systems for Java execution across different system architectures requires an understanding of program execution characteristics and the effect of system parameters on different aspects of...

    Provided By Kyushu University

  • White Papers // Nov 2012

    MD: Minimal Path-Based Fault-Tolerant Routing in On-Chip Networks

    The communication requirements of many-core embedded systems are convened by the emerging Network-on-Chip (NoC) paradigm. As on-chip communication reliability is a crucial factor in many-core systems, the NoC paradigm should address the reliability issues. Using fault-tolerant routing algorithms to reroute packets around faulty regions will increase the packet latency and...

    Provided By Kyushu University

  • White Papers // Oct 2011

    Performance Evaluations of Finite Difference Applications Realized on a Single Flux Quantum Circuits-Based Reconfigurable Accelerator

    Hardware accelerators integrating to general purpose processors are increasingly employed to achieve lower power consumption and higher processing speed, however, energy consumption of high performance accelerators has become a great issue on large scale parallel computer system. The authors have investigated the applicability of Single-Flux-Quantum (SFQ) circuits as a part...

    Provided By Kyushu University

  • White Papers // Jan 2010

    Signal Probability Control for Relieving NBTI in SRAM Cells

    Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact...

    Provided By Kyushu University

  • White Papers // Dec 2009

    Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator

    As a solution to gain high performance computation, a Large-Scale Reconfigurable Data-Path (LSRDP) processor is introduced in this paper. LSRDP is implemented by virtue of single-flux quantum circuits and integrated to a general purpose processor to accelerate the execution of Data Flow Graphs (DFGs) extracted from scientific applications. Design procedure...

    Provided By Kyushu University

  • White Papers // Sep 2006

    Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache

    In this paper, the authors propose an efficient cache line management algorithm for a Security-aware Cache architecture (SCache). SCache attempts to detect the corruption of return address values at runtime. When a return address store is executed, the cache generates a replica of the return address. This copied data is...

    Provided By Kyushu University

  • White Papers // Sep 2006

    An Energy Characterization Framework for Software-Based Embedded Systems

    In this paper, the authors propose an energy characterization framework which helps designers in developing a fast and accurate energy model for a target processor-based system. They use a linear model for energy estimation and they find the coefficients of the model using Linear Programming (LP). They use their approach...

    Provided By Kyushu University

  • White Papers // Feb 2006

    Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design

    In this paper, the authors propose a low power software design technique for processor-based embedded systems. A basic idea is to reduce switching activities in sign extension bits of instruction operands through shifting the operands. To the best of their knowledge, this is the first software-level power reduction technique which...

    Provided By Kyushu University

  • White Papers // Mar 2006

    Multiple Clustered Core Processors

    In this paper, the authors propose multiple clustered core processors as a solution that attains both low power consumption and easy programming facility. Considering the current trend of increasing power consumption and temperature, a lot of CPU venders have shipped or announced to ship multiple core processors. Especially, recent studies...

    Provided By Kyushu University

  • White Papers // Jan 2006

    A Simulation-Based Soft Error Estimation Methodology for Computer Systems

    In this paper, the authors propose a simulation-based soft error estimation methodology for computer systems. Accumulating Soft Error Rates (SERs) of all memories in a computer system results in pessimistic soft error estimation. This is because memory cells are used spatially and temporally and not all soft errors in them...

    Provided By Kyushu University

  • White Papers // Sep 2006

    A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor

    In this paper, the authors present a Reconfigurable Functional Unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The Custom Instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs...

    Provided By Kyushu University

  • White Papers // Jun 2006

    GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

    In reconfigurable systems, reconfiguration latency has a significant impact on the system performance. In this paper, a temporal partitioning algorithm is presented to partition data flow graphs for reconfigurable computing systems. Life-time of a node in a data flow graph represents the number of times it executes during the application...

    Provided By Kyushu University

  • White Papers // Jun 2006

    A Reconfigurable Functional Unit for an Adaptive Extensible Processor

    In this paper, the authors present a Reconfigurable Functional Unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication, which brings about more flexibility. The Custom Instructions (CIs) are generated deploying the hot basic blocks during the training mode....

    Provided By Kyushu University

  • White Papers // Sep 2006

    Supporting A Dynamic Program Signature: An Intrusion Detection Framework for Microprocessors

    To address computer security issues, a hardware-based intrusion detection technique is proposed. This paper uses the dynamic program execution behavior for authentication. Based on secret key information, an execution behavior is determined. Next, a secure compiler constructs object code which generates the predetermined execution behavior at runtime. During program execution,...

    Provided By Kyushu University

  • White Papers // Sep 2008

    Performance Evaluation of a Reconfigurable Instruction Set Processor

    Reconfigurable Instruction Set Processors (RISPs) introduce an effective approach for implementing embedded systems similar to Application-Specific Instruction set Processors (ASIPs) and extensible processors. Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. A combined analytical and simulation-based model is proposed and validated for performance evaluation...

    Provided By Kyushu University

  • White Papers // Dec 2010

    Custom Instructions with Multiple Exits: Generation and Execution

    In this paper, the authors propose an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. A reconfigurable functional unit is utilized to support this feature. The proposed reconfigurable functional unit is based on a matrix of functional units which is multi-cycle with the capability of...

    Provided By Kyushu University

  • White Papers // Aug 2007

    High Performance, Low Power Reconfigurable Processor for Embedded Systems

    Using an extensible processor in which Data Flow Graphs (DFGs) are generated from frequently executed portions (hot portions) of applications and are executed after chip-fabrication provides flexibility as well as addressing the time-to-market and significant nonrecurring engineering costs issues. In this paper, the effect of extending DFGs to Control Data...

    Provided By Kyushu University

  • White Papers // Dec 2011

    A Thermal-Aware Mapping Algorithm for Reducing Peak Temperature of an Accelerator Deployed in a 3D Stack

    Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has...

    Provided By Kyushu University