Leiden University

Displaying 1-14 of 14 results

  • White Papers // Jan 2014

    Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips

    The complexity of today's embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA technology make the implementation of such architectures in a single chip (MPSoC) feasible and very appealing. In recent years, the FPGA vendors integrated enormous amount of hardware resources in their...

    Provided By Leiden University

  • White Papers // Jan 2014

    Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips

    Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such architectures in a single chip feasible and very appealing. Although the FPGA chip technology is well developed by companies such as Xilinx and Altera, the concepts and the...

    Provided By Leiden University

  • White Papers // Jan 2014

    Automatic Partitioning and Mapping of Stream-Based Applications Onto the Intel IXP Network Processor

    The complexity of embedded multimedia and signal processing applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system platforms based on a single processor. Instead, multi-core or multi-processor architectures are being introduced to meet the required compute power of the...

    Provided By Leiden University

  • White Papers // Jan 2014

    Safe Execution of Untrusted Applications on Embedded Network Processors

    Controlling the function of embedded network processor systems has so far been confined to simple configuration languages and component models, with the full programming capabilities available only to trusted system-level programmers. In this paper, the authors consider a software architecture enabling the safe execution of untrusted code on the IXP1200...

    Provided By Leiden University

  • White Papers // Aug 2013

    A Runtime Adaptive H.264 Video-Decoding MPSoC Platform

    Due to current and future technology issues, multicore processing systems are required to provide support for adaptively to an ever increasing extent. This requirement may descend from demands of fault-tolerance as well as from dynamic Quality-of-Service (QoS) management strategies, depending on the targeted application and power budget. This paper presents...

    Provided By Leiden University

  • White Papers // May 2012

    Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations

    Because of the increasing complexity of modern embedded systems, High-Level Synthesis (HLS) has gained momentum. Most HLS tools employ Control Data Flow Graph (CDFG) based approaches. An alternative route from C to RTL was presented in, where a CDFG based approach was augmented with a polyhedral process network based approach....

    Provided By Leiden University

  • White Papers // Jun 2010

    Identifying Communication Models in Process Networks derived from Weakly Dynamic Programs

    Process Networks (PNs) is an appealing computation abstraction helping to specify an application in parallel form and realize it on parallel platforms. The key questions to be answered are how a PN can be derived and how its components can be realized efficiently on a given parallel system. In this...

    Provided By Leiden University

  • White Papers // Nov 2009

    Run-Time Reconfiguration of Polyhedral Process Networks Implementations

    Run-time reconfigurable computing is a novel computing paradigm which offers greater functionality with a simpler hardware design and reduced time-to-market. Although, the reconfigurable technology is constantly advancing, yet reconfigurable computing is hardly employed in real systems due to the difficulties associated with realizing and managing the reconfiguration process. In this...

    Provided By Leiden University

  • White Papers // Sep 2009

    Automatic Restructuring of Linked Data Structures

    The memory subsystem is one of the major performance bottlenecks in modern computer systems. While much effort is spent on the optimization of codes which access data regularly, not all codes will do so. Programs using pointer linked data structures are notorious for producing such so called irregular memory access...

    Provided By Leiden University

  • White Papers // Jun 2009

    The Human Processor: Changing the Relation Between Human and Computer

    In the Human-Computer Interaction (HCI) field it is common to choose the human as the task-giver and the computer as the obedient servant. HCI seeks to construct an interface between the human and the computer in such a way that the human needs to adapt as little as possible to...

    Provided By Leiden University

  • White Papers // Aug 2008

    Kahn Process Network IR Modeling for Multicore Compilation

    The complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded systems based on a single processor. Instead, emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multicore architectures. On these platforms two major problems emerge: how to design...

    Provided By Leiden University

  • White Papers // Sep 2007

    Bounded CCA2-Secure Encryption

    Encryption is often compared to a 'Secure envelope'. Whereas encryption schemes withstanding passive Chosen Plaintext Attacks (CPA) can be constructed based on a variety of computational assumptions, only a few assumptions are known to imply the existence of encryption schemes withstanding adaptive Chosen-Ciphertext Attacks (CCA2). Towards addressing this asymmetry, the...

    Provided By Leiden University

  • White Papers // May 2007

    Customizing Reconfigurable On-Chip Crossbar Scheduler

    The authors present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to logical topologies for given applications. Considering conventional fully parallel and sequential schedulers as reference designs, a comparative performance analysis is conducted. The hardware scheduler module...

    Provided By Leiden University

  • White Papers // Sep 2006

    An Iterative Approach to Area and Performance Optimization for Superscalar Processors

    When designing embedded systems, one needs to make decisions concerning the different components that will be included in a microprocessor. An important issue in this phase is the chip area vs. performance tradeo. In this paper, the authors investigate the relationship between chip area and performance for superscalar microprocessors. They...

    Provided By Leiden University

  • White Papers // Sep 2009

    Automatic Restructuring of Linked Data Structures

    The memory subsystem is one of the major performance bottlenecks in modern computer systems. While much effort is spent on the optimization of codes which access data regularly, not all codes will do so. Programs using pointer linked data structures are notorious for producing such so called irregular memory access...

    Provided By Leiden University

  • White Papers // Jan 2014

    Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips

    Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such architectures in a single chip feasible and very appealing. Although the FPGA chip technology is well developed by companies such as Xilinx and Altera, the concepts and the...

    Provided By Leiden University

  • White Papers // Aug 2013

    A Runtime Adaptive H.264 Video-Decoding MPSoC Platform

    Due to current and future technology issues, multicore processing systems are required to provide support for adaptively to an ever increasing extent. This requirement may descend from demands of fault-tolerance as well as from dynamic Quality-of-Service (QoS) management strategies, depending on the targeted application and power budget. This paper presents...

    Provided By Leiden University

  • White Papers // Jun 2010

    Identifying Communication Models in Process Networks derived from Weakly Dynamic Programs

    Process Networks (PNs) is an appealing computation abstraction helping to specify an application in parallel form and realize it on parallel platforms. The key questions to be answered are how a PN can be derived and how its components can be realized efficiently on a given parallel system. In this...

    Provided By Leiden University

  • White Papers // Nov 2009

    Run-Time Reconfiguration of Polyhedral Process Networks Implementations

    Run-time reconfigurable computing is a novel computing paradigm which offers greater functionality with a simpler hardware design and reduced time-to-market. Although, the reconfigurable technology is constantly advancing, yet reconfigurable computing is hardly employed in real systems due to the difficulties associated with realizing and managing the reconfiguration process. In this...

    Provided By Leiden University

  • White Papers // Jan 2014

    Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips

    The complexity of today's embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA technology make the implementation of such architectures in a single chip (MPSoC) feasible and very appealing. In recent years, the FPGA vendors integrated enormous amount of hardware resources in their...

    Provided By Leiden University

  • White Papers // May 2007

    Customizing Reconfigurable On-Chip Crossbar Scheduler

    The authors present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to logical topologies for given applications. Considering conventional fully parallel and sequential schedulers as reference designs, a comparative performance analysis is conducted. The hardware scheduler module...

    Provided By Leiden University

  • White Papers // Jan 2014

    Safe Execution of Untrusted Applications on Embedded Network Processors

    Controlling the function of embedded network processor systems has so far been confined to simple configuration languages and component models, with the full programming capabilities available only to trusted system-level programmers. In this paper, the authors consider a software architecture enabling the safe execution of untrusted code on the IXP1200...

    Provided By Leiden University

  • White Papers // Sep 2007

    Bounded CCA2-Secure Encryption

    Encryption is often compared to a 'Secure envelope'. Whereas encryption schemes withstanding passive Chosen Plaintext Attacks (CPA) can be constructed based on a variety of computational assumptions, only a few assumptions are known to imply the existence of encryption schemes withstanding adaptive Chosen-Ciphertext Attacks (CCA2). Towards addressing this asymmetry, the...

    Provided By Leiden University

  • White Papers // Aug 2008

    Kahn Process Network IR Modeling for Multicore Compilation

    The complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded systems based on a single processor. Instead, emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multicore architectures. On these platforms two major problems emerge: how to design...

    Provided By Leiden University

  • White Papers // Jan 2014

    Automatic Partitioning and Mapping of Stream-Based Applications Onto the Intel IXP Network Processor

    The complexity of embedded multimedia and signal processing applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system platforms based on a single processor. Instead, multi-core or multi-processor architectures are being introduced to meet the required compute power of the...

    Provided By Leiden University

  • White Papers // Sep 2006

    An Iterative Approach to Area and Performance Optimization for Superscalar Processors

    When designing embedded systems, one needs to make decisions concerning the different components that will be included in a microprocessor. An important issue in this phase is the chip area vs. performance tradeo. In this paper, the authors investigate the relationship between chip area and performance for superscalar microprocessors. They...

    Provided By Leiden University

  • White Papers // Jun 2009

    The Human Processor: Changing the Relation Between Human and Computer

    In the Human-Computer Interaction (HCI) field it is common to choose the human as the task-giver and the computer as the obedient servant. HCI seeks to construct an interface between the human and the computer in such a way that the human needs to adapt as little as possible to...

    Provided By Leiden University

  • White Papers // May 2012

    Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations

    Because of the increasing complexity of modern embedded systems, High-Level Synthesis (HLS) has gained momentum. Most HLS tools employ Control Data Flow Graph (CDFG) based approaches. An alternative route from C to RTL was presented in, where a CDFG based approach was augmented with a polyhedral process network based approach....

    Provided By Leiden University