North Carolina State University

Displaying 201-217 of 217 results

  • White Papers // Jan 2009

    PFetch: Software Prefetching Exploiting Temporal Predictability of Memory Access Streams

    CPU speeds have increased faster than the rate of improvement in memory access latencies in the recent past. As a result, with programs that suffer excessive cache misses, the CPU will increasingly be stalled waiting for the memory system to provide the requested memory line. Prefetching is a latency hiding...

    Provided By North Carolina State University

  • White Papers // Sep 2008

    Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

    Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound Worst-Case Execution Time (WCET) bounds of tasks. Designers of these systems are forced to avoid state-of-the-art processors due to their inherent architectural complexity (such as out-of-order...

    Provided By North Carolina State University

  • White Papers // Aug 2008

    Security-Aware Resource Optimization in Distributed Service Computing

    In this paper, the authors consider a set of computer resources used by a service provider to host enterprise applications for customer services subject to a Service Level Agreement (SLA). The SLA defines three QoS metrics, namely, trustworthiness, percentile response time and availability. They first give an overview of current...

    Provided By North Carolina State University

  • White Papers // Jul 2008

    Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures

    In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distinct threads differ, but each thread may also present diversity in its performance and resource usage over time. A heterogeneous Chip Multi-Processor (CMP) architecture consists of processor cores...

    Provided By North Carolina State University

  • White Papers // Jul 2008

    Performance Assessment and Compensation for Secure Networked Control Systems

    Network-Control-Systems (NCS) have been gaining popularity due to their high potential in widespread applications and becoming realizable due to the rapid advancements in embedded systems, wireless communication technologies. This paper addresses the issue of NCS information security as well its time-sensitive performance and their trade-off. A PI controller implemented on...

    Provided By North Carolina State University

  • White Papers // Jul 2008

    Exploiting Locality to Ameliorate Packet Queue Contention and Serialization

    Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, multiple processors are used to overlap the processing of multiple packets. Packet queuing - the fundamental mechanism enabling packet scheduling, differentiated services, and traffic isolation - requires a read-modify-write...

    Provided By North Carolina State University

  • White Papers // Mar 2008

    Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

    Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of Worst-Case Execution Time (WCET) bounds is a critical...

    Provided By North Carolina State University

  • White Papers // Nov 2007

    Worst-Case Execution Time Analysis of Security Policies for Deeply Embedded Real-Time Systems

    Deeply embedded systems often have unique constraints because of their small size and vital roles in critical infrastructure. Problems include limitations on code size, limited access to the actual hardware, etc. These problems become more critical in real-time systems where security policies must not only work within the above limitations...

    Provided By North Carolina State University

  • White Papers // May 2007

    Fused Two-Level Branch Prediction with Ahead Calculation

    In this paper, the authors propose a Fused Two-Level (FTL) branch predictor combined with an ahead calculation method. The FTL predictor is derived from the fusion hybrid predictor. It achieves high accuracy by adopting PA p-based GEometrical History Length (GEHL) prediction, which is an effective prediction scheme exploiting local histories....

    Provided By North Carolina State University

  • White Papers // Apr 2007

    Conformance Checking of Access Control Policies Specified in XACML

    Access control is one of the most fundamental and widely used security mechanisms. Access control mechanisms control which principals such as users or processes have access to which resources in a system. To facilitate managing and maintaining access control, access control policies are increasingly written in specification languages such as...

    Provided By North Carolina State University

  • White Papers // Apr 2007

    Information Security with Real-Time Operation: Performance Assessment for Next Generation Wireless Distributed Networked-Control-Systems

    Distributed Network-Control-Systems (D-NCS) are a multidisciplinary effort whose aim is to produce a network structure and components that are capable of integrating sensors, actuators, communication, and control algorithms in a manner to suit real-time applications. They have been gaining popularity due to their high potential in widespread applications and becoming...

    Provided By North Carolina State University

  • White Papers // Feb 2007

    The ChoicePoint Dilemma: How Data Brokers Should Handle the Privacy of Personal Information

    In 2005, there was a significant increase in the number of security and privacy breaches disclosed to the public. Leading the charge was ChoicePoint, a data broker that suffered fraudulent access to its vast databases of personal information. ChoicePoint and other data brokers exist in a largely unregulated environment, in...

    Provided By North Carolina State University

  • White Papers // Jan 2007

    Using Deception to Hide Things from Hackers: Processes, Principles, and Techniques

    Deception offers one means of hiding things from an adversary. This paper introduces a model for understanding, comparing and developing methods of deceptive hiding. The model characterizes deceptive hiding in terms of how it defeats the underlying processes that an adversary uses to discover the hidden thing. An adversary's process...

    Provided By North Carolina State University

  • White Papers // Aug 2006

    The State of ZettaRAM

    Computer architectures are heavily influenced by parameters imposed by memory technologies. Memory hierarchies, virtual memory, prefetching, multithreading, and large-window processors are some well-known examples of architectural innovations influenced by memory constraints. This paper surveys ZettaRAM, a nascent memory technology based on molecular electronics. From patents and papers, the authors distill...

    Provided By North Carolina State University

  • White Papers // Aug 2006

    Assertion-Based Microarchitecture Design for Improved Fault Tolerance

    Protection against transient faults is an important constraint in high-performance processor design. One strategy for achieving efficient reliability is to apply targeted fault checking/masking techniques to different units within an overall reliability regimen. In this paper, the authors propose a novel class of targeted fault checks that verify the functioning...

    Provided By North Carolina State University

  • White Papers // Jun 2006

    A Framework for Identifying Compromised Nodes in Sensor Networks

    Sensor networks are often subject to physical attacks. Once a node's cryptographic key is compromised, an attacker may completely impersonate it, and introduce arbitrary false information into the network. Basic cryptographic security mechanisms are often not effective in this situation. Most techniques to address this problem focus on detecting and...

    Provided By North Carolina State University

  • White Papers // Jan 2006

    Non-Uniform Program Analysis & Repeatable Execution Constraints: Exploiting Out-of-Order Processors in Real-Time Systems

    In this paper the authors enable easy, tight, and safe timing analysis of contemporary complex processors. They exploit the fact that out-of-order processors can be analyzed via simulation in the absence of variable control-flow. In their first technique, Non-Uniform Program Analysis (NUPA), program segments with a single flow of control...

    Provided By North Carolina State University

  • White Papers // Jan 2014

    IPSec/VPN Security Policy: Correctness, Conflict Detection and Resolution

    IPSec (Internet Security Protocol suite) functions will be executed correctly only if its policies are correctly specified and configured. Manual IPSec policy configuration is inefficient and error-prone. An erroneous policy could lead to communication blockade or serious security breach. In addition, even if policies are specified correctly in each domain,...

    Provided By North Carolina State University

  • White Papers // Feb 2013

    Directory-Oblivious Capacity Sharing in Tiled CMPs

    In bus-based CMPs with private caches, Capacity Sharing is applied by spilling victim cache blocks from over-utilized caches to under-utilized ones. If a spilled block is needed, it can be retrieved by posting a miss on the bus. Prior work in this domain focused on Capacity Sharing design and put...

    Provided By North Carolina State University

  • White Papers // Jan 2013

    Flexible Capacity Partitioning in Many-Core Tiled CMPs

    Chip Multi-Processors (CMP) have become a mainstream computing platform. As transistor density shrinks and the number of cores increases, more scalable CMP architectures will emerge. Recently, tiled architectures have shown such scalable characteristics and been used in many industry chips. The memory hierarchy in tiled architectures presents interesting design challenges....

    Provided By North Carolina State University

  • White Papers // Feb 2012

    Evaluating Dynamics and Bottlenecks of Memory Collaboration in Cluster Systems

    With the fast development of highly-integrated distributed systems (cluster systems), designers face interesting memory hierarchy design choices while attempting to avoid the notorious disk swapping. Swapping to the free remote memory through Memory Collaboration has demonstrated its cost-effectiveness compared to over-provisioning the cluster for peak load requirements. Recent memory collaboration...

    Provided By North Carolina State University

  • White Papers // Feb 2012

    Data Sharing in MultiThreaded Applications and Its Impact on Chip Design

    Analytical modeling is becoming an increasingly important technique used in the design of chip multiprocessors. Most such models assume multi-programmed workload mixes and either ignore or oversimplify the behavior of multi-threaded applications. In particular, data sharing observed in multi-threaded applications, and its impact on chip design decisions, has not been...

    Provided By North Carolina State University

  • White Papers // Jan 2011

    Impact of Data Sharing on CMP Design: A Study Based on Analytical Modeling

    Over the past few years, Chip Multi Processor (CMP) architecture has become the dominating hardware architecture across a spectrum of computing machinery - personal computing devices, workstations, commercial and scientific servers, and warehouse scale computers. The sheer complexity involved in the design and verification of each unit in a CMP...

    Provided By North Carolina State University

  • White Papers // Dec 2010

    Architectural Framework for Supporting Operating System Survivability

    The ever increasing size and complexity of Operating System (OS) kernel code bring an inevitable increase in the number of security vulnerabilities that can be exploited by attackers. A successful security attack on the kernel has a profound impact that may affect all processes running on it. In this paper,...

    Provided By North Carolina State University

  • White Papers // Dec 2009

    Defining Anomalous Behavior for Phase Change Memory

    Traditional memory systems based on memory technologies such as DRAM are fast approaching their cost and power limits. Alternative memory technologies such as Phase Change Memory (PCM) are being widely researched as a scalable, cost- and power-efficient alternative for DRAM. However, a PCM memory cell has a limited endurance of...

    Provided By North Carolina State University

  • White Papers // May 2012

    Understanding the Limits of Capacity Sharing in CMP Private Caches

    Chip Multi Processor (CMP) systems present interesting design challenges at the lower levels of the cache hierarchy. Private L2 caches allow easier processor-cache design reuse, thus scaling better than a system with a shared L2 cache, while offering better performance isolation and lower access latency. While some private cache management...

    Provided By North Carolina State University

  • White Papers // Sep 2009

    Memory Management Thread for Heap Allocation Intensive Sequential Applications

    Dynamic memory management is one of the most ubiquitous and expensive operations in many C/C++ applications. Some C/C++ programs might spend up to one third of their execution time in dynamic memory management routines. With multicore processors as a mainstream architecture, it is important to investigate how dynamic memory management...

    Provided By North Carolina State University

  • White Papers // Feb 2014

    Understanding the Tradeoffs Between Software-Managed Vs. Hardware-Managed Caches in GPUs

    On-chip caches are commonly used in computer systems to hide long off-chip memory access latencies. To manage on-chip caches, either software-managed or hardware-managed schemes can be employed. State-of-art accelerators, such as the NVIDIA Fermi or Kepler GPUs and Intel's forthcoming MIC \"KNights Landing\" (KNL), support both software-managed caches, aka. shared...

    Provided By North Carolina State University

  • White Papers // Jan 2014

    Warp-Level Divergence in GPUs: Characterization, Impact, and Mitigation

    High throughput architectures rely on high Thread-Level Parallelism (TLP) to hide execution latencies. In state-of-art Graphics Processing Units (GPUs), threads are organized in a grid of Thread Blocks (TBs) and each TB contains tens to hundreds of threads. With a TB-level resource management scheme, all the resource required by a...

    Provided By North Carolina State University

  • White Papers // Jun 2012

    Fixing Performance Bugs: An Empirical Study of Open-Source GPGPU Programs

    Given the extraordinary computational power of modern Graphics Processing Units (GPUs), general purpose computation on GPUs (GPGPU) has become an increasingly important platform for high performance computing. To better understand how well the GPU resource has been utilized by application developers and then to facilitate them to develop high performance...

    Provided By North Carolina State University

  • White Papers // Feb 2013

    Adaptive Cache Bypassing for Inclusive Last Level Caches

    Cache hierarchy designs, including bypassing, replacement, and the inclusion property, have significant performance impact. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the Last Level Cache (LLC) performance. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing...

    Provided By North Carolina State University

  • White Papers // Feb 2012

    Locality Principle Revisited: A Probability-Based Quantitative Approach

    This paper revisits the fundamental concept of the locality of references and proposes to quantify it as a conditional probability: in an address stream, given the condition that an address is accessed, how likely the same address (temporal locality) or an address within its neighborhood (spatial locality) will be accessed...

    Provided By North Carolina State University

  • White Papers // Feb 2012

    CPU-Assisted GPGPU on Fused CPU-GPU Architectures

    This paper presents a novel approach to utilize the CPU resource to facilitate the execution of GPGPU programs on fused CPU-GPU architectures. In the authors' model of fused architectures, the GPU and the CPU are integrated on the same die and share the on-chip L3 cache and off-chip memory, similar...

    Provided By North Carolina State University

  • White Papers // Jan 2011

    Time-Ordered Event Traces: A New Debugging Primitive for Concurrency Bugs

    Non-determinism makes concurrent bugs extremely difficult to reproduce and to debug. In this paper, the authors propose a new debugging primitive to facilitate the debugging process by exposing this non-deterministic behavior to the programmer. The key idea is to generate a time-ordered trace of events such as function calls/returns and...

    Provided By North Carolina State University