Pontifical Catholic University of Rio de Janeiro

Displaying 1-40 of 62 results

  • White Papers // Jan 2014

    A Monitored NoC with Runtime Path Adaptation

    Network-on-Chips (NoCs) are already a common choice of communication infrastructure for complex System-on-Chips (SoCs) containing a large number of processing resources and with critical communication requirements. A NoC provides several advantages, such as higher scalability, efficient energy management, higher bandwidth and lower average latency, when compared to bus-based systems. Experiments...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    Tool-Set for NoC-Based MPSoC Debugging - A Protocol View Perspective

    Software development becomes an important issue in today's MPSoC design. Due to the inherent non-deterministic behavior of MPSoCs, they are prone to concurrency bugs. Debugging tools for MPSoC may be grouped in the following classes: simulators, parallel software development environments, NoC debuggers. An important gap is observed concerning a complete...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    A Framework for MPSoC Generation and Distributed Applications Evaluation

    The huge design space to develop the hardware/software infrastructure of MPSoCs (Multi-Processor System-on-Chip), or to evaluate the performance of applications requires frameworks able to generate and to simulate the MPSoC. The design of MPSoCs is a complex task. From the designer side point of view, a new feature inserted into...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    Runtime Fault Recovery Protocol for NoC-Based MPSoCs

    The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This paper presents a novel fault-tolerant communication protocol that...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    Wrapper Design for the Reuse of Functional Interconnect for Test

    In this paper, the authors propose a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. They demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Dec 2013

    Evaluating the Trade-Off Between DVFS Energy-Savings and Virtual Networks Performance

    Data centers usually employ virtualization techniques coupled with other techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), in order to reduce overall energy consumption. However, changes in processor frequency may impact the network performance, specifically in metrics such as throughput and jitter. This paper evaluates the trade-off between changes...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2013

    Phoenix NoC: A Distributed Fault Tolerant Architecture

    The advances in deep submicron technology have made the development of large Multi-Processor System-on-Chip (MPSoC) possible and Network-on-Chips (NoCs) have been recognized to provide efficient communication architecture for such systems. With the positive effects on the device's integration some drawbacks arise, such as the increase of fault susceptibility during the...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2013

    Adaptive QoS Techniques for NoC-Based MPSoCs

    With the significant increase in the number of processing elements in NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and QoS guarantees. The main gap observed in the NoC-based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2013

    Achieving QoS in NoC-Based MPSoCs Through Dynamic Frequency Scaling

    The management of Quality-of-Service (QoS) constraints in NoC-based MPSoCs, with dozens of tasks running simultaneously, is still a challenge. Techniques applied at design or run-time to address this issue adopts different QoS metrics. Designers include in their systems monitoring techniques, adapting at run-time the QoS parameters to cope with the...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2013

    Evaluating the Scalability of Test Buses

    Intra-chip communication architectures evolved from buses to networks-on-chip, in order to provide design scalability and increased bandwidth. However, the predominant test architecture for SoCs is still based on buses. While this approach presents advantages, such as simple design and a mature set of automation tools, its scalability is questionable. This...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2013

    TSV Multiplexing: A 3D NoC Occupancy Analysis

    Network-on-Chips (NoCs) are proposed as promising packet-based communication platforms for Multi-Processor System-on-Chip (MPSoC) design, due to scalability, better throughput and reduced power consumption. NoC-based architectures are characterized by various trade-offs with regard to structural characteristics, performance specifications, and application demands. However, increasing the number of cores over a 2D plane...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2013

    LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries

    Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower design complexity through the use of pre-designed and pre-characterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. In this paper, modeling of...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2013

    Determining the Test Sources/Sinks for NoC TAMs

    Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2013

    Distributed Resource Management in NoC-Based MPSoCs with Dynamic Cluster Sizes

    Scalability is an important issue in large MPSoCs. MPSoCs may execute several applications in parallel, with dynamic workload, and tight QoS constraints. Thus, the MPSoC management must be distributed to cope with such constraints. In this paper, the authors present a distributed resource management in NoC-based MPSoC, using a clustering...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Mar 2013

    ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design

    The asynchronous circuit design paradigm provides a practical solution for several challenges and constraints of current and future technologies to build integrated circuits and systems. However, there is little electronic design automation support for this paradigm. This work presents a standard cell library designed to support a semi-custom approach in...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2012

    Power-Efficient Design of a Clockless NoC Router with a New Integrated Flow

    The downscaling of silicon technology and the capacity to build entire systems on a chip has made intrachip communication a relevant research topic. Besides, technology challenges point to the fast adoption of non-synchronous Network-on-Chips (NoCs), using either Globally Asynchronous, Locally Synchronous (GALS) or even clockless approaches. However, clockless circuit design...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2012

    Enhancing Performance of MPSoCs Through Distributed Resource Management

    The constant growth in the number of cores in SoCs implies an important issue: scalability. NoC-based MPSoCs offer scalability at the hardware level. However, the management of the MPSoC resources requires also scalable methods, to effectively extract the computational power offered by dozens of processors. State-of-the-art proposals adopt different approaches...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2012

    Evaluation of Adaptive Management Techniques in NoC-Based MPSoCs

    Self-adaptation capability is as a key feature to meet runtime application requirements in dynamic systems such as NoC-based MPSoCs. In this paper, the authors present an evaluation of adaptive management techniques combined with task monitoring, which is able to change at runtime the communication priority, the tasks scheduling priority and...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2012

    Performance Evaluation of Container-Based Virtualization for High Performance Computing Environments

    The use of virtualization technologies in High Performance Computing (HPC) environments has traditionally been avoided due to their inherent performance overhead. However, with the rise of container-based virtualization implementations, such as Linux VServer, OpenVZ and LinuX Containers (LXC), it is possible to obtain a very low overhead leading to near...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2012

    Mazenoc: Novel Approach for Fault-Tolerant NoC Routing

    In this paper, the authors present an original approach to define a path between two routers in a NoC with faulty routers. Current state-of-the-art adopts non-scalable solutions, using tables to store paths, or distributed approaches that keep the status of neighbor routers. The proposed approach searched its foundations in the...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2012

    Power Consumption Reduction in MPSoCs Through DFS

    The use of power management techniques is mandatory in embedded devices, which must provide high performance with low energy consumption. Due to the high variability present in the applications workload executed by these devices, this management should be executed dynamically. The use of traditional Dynamic Voltage and Frequency Scaling (DVFS)...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2012

    Scheduling MapReduce Jobs in HPC Clusters

    MapReduce (MR) has become a de facto standard for large-scale data analysis. Moreover, it has also attracted the attention of the HPC community due to its simplicity, efficiency and highly scalable parallel model. However, MR implementations present some issues that may complicate its execution in existing HPC clusters, especially concerning...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2012

    A Fast, Memory Efficient, Scalable and Multilingual Dictionary Retrievera

    In this paper, the authors present a novel approach to deal with dictionary retrieval. This paper is based on a very efficient and scalable theoretical structure called Multi-Terminal Multi-valued Decision Diagrams (MTMDD). Such tool allows the definition of very large, even multilingual, dictionaries without significant increase in memory demands, and...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2012

    Proposal and Evaluation of a Task Migration Protocol for NoC-Based MPSoCs

    Task migration is a well-known strategy adopted in distributed systems for load balancing. But the adoption of such strategy in NoC-based MPSoC is scarce in the literature. This paper proposes a complete task migration protocol for NoC-based MPSoCs. The migration transfers the task code, data and context to another PE....

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2011

    On the Relevance of Code Anomalies for Identifying Architecture Degradation Symptoms

    The longevity of evolving software systems largely depends on their resilience to architectural design degradation. It is often assumed that code anomalies are always key indicators of architecture degradation symptoms. The problem is that there is still limited knowledge about the circumstances under which code anomalies represent architectural problems. Without...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2011

    Exploring Heterogeneous NoC-Based MPSoCs: From FPGA to High-Level Modeling

    In this paper, the authors propose a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. They propose a solution that uses a unified model-based framework, which is calibrated according to...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2011

    PL-AspectualACME: An Aspect-Oriented Architectural Description Language for Software Product Lines

    Software Product Line (SPL) development typically relies on feature models to represent the commonalities and variabilities of a family of software products. Although feature models play an important role in describing SPL elements, they are limited to provide high-level feature decompositions that do not explicitly represent the SPL architecture. To...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2011

    Towards a Suite of Metrics for Advanced Composition Mechanisms

    Software composition defines the interaction between two or more modules. Advanced programming techniques, such as aspect-oriented programming and feature-oriented programming, support a wide range of expressive composition mechanisms that promote a shift in the structure of programs: while complexity is presumably factored out of software modules, their composition code becomes...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2011

    Core Communication Interface for FPGAs

    The use of pre-designed and pre-verified complex hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2011

    Maximum Migration Time Guarantees in Dynamic Server Consolidation for Virtualized Data Centers

    Server consolidation is a vital mechanism in modern data centers in order to minimize expenses with infrastructure. In most cases, server consolidation may require migrating virtual machines between different physical servers. Although the downtime of live-migration is negligible, the amount of time to migrate all virtual machines can be substantial,...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2011

    Server Consolidation With Migration Control for Virtualized Data Centers

    Virtualization has become a key technology for simplifying service management and reducing energy costs in data centers. One of the challenges faced by data centers is to decide when, how, and which Virtual Machines (VMs) have to be consolidated into a single physical server. Server consolidation involves VM migration, which...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    The Impact of Coupling on the Fault-Proneness of Aspect-Oriented Programs: An Empirical Study

    Coupling in software applications is often used as an indicator of external quality attributes such as fault-proneness. In fact, the correlation of coupling metrics and faults in object-oriented programs has been widely studied. However, there is very limited knowledge about which coupling properties in Aspect-Oriented Programming (AOP) are effective indicators...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    Identifying Code Smells With Multiple Concern Views

    Code smells are anomalies often caused by the way concerns are realized in the source code. Their identification might depend on properties governing the structure of individual concerns and their inter-dependencies in the system implementation. Although code visualization tools are increasingly applied to support anomaly detection, they are mostly limited...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    Characterising Faults in Aspect-Oriented Programs: Towards Filling the Gap Between Theory and Practice

    Since the proposal of Aspect-Oriented Programming, several candidate fault taxonomies for Aspect-Oriented (AO) software have been proposed. Such taxonomies, however, generally rely on language features, hence still requiring practical evaluation based on realistic implementation scenarios. The current lack of available AO systems for evaluation as well as historical data are...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2010

    History-Sensitive Recovery of Product Line Features

    Since Software Product Lines (SPLs) increasingly have to satisfy additional requirements, their designs might degenerate over time. The degeneration is caused by various reasons. For instance, the features suddenly start to be realized and they evolved in inconsistent ways across multiple products. In an extreme case, the SPL code is...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Analyzing Crosscutting Exception Flows in an Evolving System

    The presence of global exceptions often has a harmful impact on a software system in terms of maintainability and reliability. Global exception flows affect interfaces of different methods in different classes and packages, and their handling policies are scattered through these modules. Reasoning about exception flows is even more complicated...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Optimization Under Uncertainty For Operational Planning Of Petroleum Refineries

    In this paper, author describe a Nonlinear Programming (NLP) model for operational planning of oil refineries, considering uncertainties related to oil supply and refinery capacity. Three mathematical models based on stochastic programming (two-stage stochastic model) and robust programming (min-max regret model and max-min model) are developed to address these uncertainties....

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Analyzing the Effects of Aspect Properties on Model Composition Effort: A Replicated Study

    Nowadays there are an increasing number of researchers who have focusing on defining and improving model composition techniques. This can be related to the fact that model composition is playing a main role on model-driven software engineering. Model composition can be viewed as an operation where a set of activities...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2010

    Model Based Approach for Heterogeneous Application Modelling for Real Time Embedded Systems

    Modeling and simulation are essential methods in state of the art embedded system design. Especially, modeling at high levels of abstraction helps designers to handle the design complexity and heterogeneity. This paper presents a model based approach for modeling and validation of heterogeneous application together with a multicore Network-on-Chip (NoC)...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2010

    Hermes-A - An Asynchronous NoC Router with Distributed Routing

    Interest in asynchronous circuits has increased due the growing limitations faced during the design of synchronous System-on-Chip (SoC) circuits, which often result in over constrained design and operation. However, asynchronous Computer Aided Design (CAD) tools still have to undergo a long evolutionary path before being accepted by most designers. The...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Optimization Under Uncertainty For Operational Planning Of Petroleum Refineries

    In this paper, author describe a Nonlinear Programming (NLP) model for operational planning of oil refineries, considering uncertainties related to oil supply and refinery capacity. Three mathematical models based on stochastic programming (two-stage stochastic model) and robust programming (min-max regret model and max-min model) are developed to address these uncertainties....

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2011

    Server Consolidation With Migration Control for Virtualized Data Centers

    Virtualization has become a key technology for simplifying service management and reducing energy costs in data centers. One of the challenges faced by data centers is to decide when, how, and which Virtual Machines (VMs) have to be consolidated into a single physical server. Server consolidation involves VM migration, which...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2009

    Multi-View Composition Language for Software Product Line Requirements

    Composition of requirements models in Software Product Line (SPL) development enables stakeholders to derive the requirements of target software products and, very important, to reason about them. Given the growing complexity of SPL development and the various stakeholders involved, their requirements are often specified from heterogeneous, partial views. However, existing...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2009

    Assessment of the Design Modularity and Stability of Multi-Agent System Product Lines

    A Multi-Agent System Product Line (MAS-PL) defines an architecture whose design and implementation is accomplished using software agents to address its common and variable features. MAS-PL promotes the large-scale reuse of common and variable agency features across multiple MAS applications. The development of MAS-PLs can be achieved through MAS-specific platforms...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2009

    Variability Management in Aspect-Oriented Architecture Description Languages: An Integrated Approach

    In this paper, the authors propose an integrated approach for managing variabilities in architectural specifications of software product lines. Their approach combines an aspect-oriented architectural description language for product lines, PL-AspectualACME, with a variability modeling language, VML4Arch. PL-AspectualACME, also proposed in this paper, is used to specify the overall architectural...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2009

    Coupling Metrics for Aspect-Oriented Programming: A Systematic Review of Maintainability Studies

    Over the last few years, a growing number of studies have explored how Aspect-Oriented Programming (AOP) might impact software maintainability. Most of the studies use coupling metrics to assess the impact of AOP mechanisms on maintainability attributes such as design stability. Unfortunately, the use of such metrics is fraught with...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2009

    Comparing Stability of Implementation Techniques for Multi-Agent System Product Lines

    Multi-Agent Systems (MAS) are increasingly being exploited to support autonomous recommendation of products and information to contemporary application users. Multi-Agent System Product Lines (MAS-PL) promote large-scale reuse of common and variable agency features across multiple MAS applications. The development of MAS-PLs can be achieved through alternative MAS-specific frameworks (JADE and...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    The Impact of Coupling on the Fault-Proneness of Aspect-Oriented Programs: An Empirical Study

    Coupling in software applications is often used as an indicator of external quality attributes such as fault-proneness. In fact, the correlation of coupling metrics and faults in object-oriented programs has been widely studied. However, there is very limited knowledge about which coupling properties in Aspect-Oriented Programming (AOP) are effective indicators...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2010

    History-Sensitive Recovery of Product Line Features

    Since Software Product Lines (SPLs) increasingly have to satisfy additional requirements, their designs might degenerate over time. The degeneration is caused by various reasons. For instance, the features suddenly start to be realized and they evolved in inconsistent ways across multiple products. In an extreme case, the SPL code is...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    Identifying Code Smells With Multiple Concern Views

    Code smells are anomalies often caused by the way concerns are realized in the source code. Their identification might depend on properties governing the structure of individual concerns and their inter-dependencies in the system implementation. Although code visualization tools are increasingly applied to support anomaly detection, they are mostly limited...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2010

    Characterising Faults in Aspect-Oriented Programs: Towards Filling the Gap Between Theory and Practice

    Since the proposal of Aspect-Oriented Programming, several candidate fault taxonomies for Aspect-Oriented (AO) software have been proposed. Such taxonomies, however, generally rely on language features, hence still requiring practical evaluation based on realistic implementation scenarios. The current lack of available AO systems for evaluation as well as historical data are...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Analyzing Crosscutting Exception Flows in an Evolving System

    The presence of global exceptions often has a harmful impact on a software system in terms of maintainability and reliability. Global exception flows affect interfaces of different methods in different classes and packages, and their handling policies are scattered through these modules. Reasoning about exception flows is even more complicated...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2010

    Analyzing the Effects of Aspect Properties on Model Composition Effort: A Replicated Study

    Nowadays there are an increasing number of researchers who have focusing on defining and improving model composition techniques. This can be related to the fact that model composition is playing a main role on model-driven software engineering. Model composition can be viewed as an operation where a set of activities...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2009

    Empirical Evaluation of Effort on Composing Design Models

    The importance of model composition in model-centric software development is recognized by researchers and practitioners. However, the lack of empirical evidence about the impact of model composition techniques on developers' effort is a key impairment for their adoption in real-world design settings. Software engineers are left without any guidance on...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2010

    Stability of Product Lines With Composition Filters: An Exploratory Study

    With system development becoming increasingly incremental, design stability stands out as one of the most desirable software quality attributes. Development of stable software systems is particularly challenging in the domain of Software Product Lines (SPLs), where their core architecture, set of features, and multiple products are continuously evolving. Contemporary programming...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Mar 2010

    Evaluating Composition Techniques for Architectural Specifications: A Comparative Study

    Techniques for composing architectural specifications are emerging in order to facilitate software architecture evolution. However, there is little empirical understanding on whether such techniques scale when they are used to express different types of architectural changes. This paper presents a first comparative evaluation of two significantly-different composition techniques for architectural...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2010

    ASPECT-MONITOR an Aspect-Based Approach to WS-Contract Monitoring

    Contract monitoring is carried out to ensure the Quality of Services (QoS) attributes and levels specified in an electronic contract throughout a business process enactment. This paper proposes an approach to improve QoS monitoring based on the aspect-oriented paradigm. Monitoring concerns are encapsulated into aspects to be executed when specific...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2011

    Towards a Suite of Metrics for Advanced Composition Mechanisms

    Software composition defines the interaction between two or more modules. Advanced programming techniques, such as aspect-oriented programming and feature-oriented programming, support a wide range of expressive composition mechanisms that promote a shift in the structure of programs: while complexity is presumably factored out of software modules, their composition code becomes...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2011

    PL-AspectualACME: An Aspect-Oriented Architectural Description Language for Software Product Lines

    Software Product Line (SPL) development typically relies on feature models to represent the commonalities and variabilities of a family of software products. Although feature models play an important role in describing SPL elements, they are limited to provide high-level feature decompositions that do not explicitly represent the SPL architecture. To...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Nov 2011

    On the Relevance of Code Anomalies for Identifying Architecture Degradation Symptoms

    The longevity of evolving software systems largely depends on their resilience to architectural design degradation. It is often assumed that code anomalies are always key indicators of architecture degradation symptoms. The problem is that there is still limited knowledge about the circumstances under which code anomalies represent architectural problems. Without...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2009

    Automating the Product Derivation Process of Multi-Agent Systems Product Lines

    Agent-oriented software engineering and software product lines are two promising software engineering techniques. Recent research work explores the integration between them to allow reuse and variability management in the context of complex systems. However, the automatic product derivation process is not addressed in the current literature. In this paper, the...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Aug 2012

    Performance Evaluation of Container-Based Virtualization for High Performance Computing Environments

    The use of virtualization technologies in High Performance Computing (HPC) environments has traditionally been avoided due to their inherent performance overhead. However, with the rise of container-based virtualization implementations, such as Linux VServer, OpenVZ and LinuX Containers (LXC), it is possible to obtain a very low overhead leading to near...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2013

    Adaptive QoS Techniques for NoC-Based MPSoCs

    With the significant increase in the number of processing elements in NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and QoS guarantees. The main gap observed in the NoC-based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    A Framework for MPSoC Generation and Distributed Applications Evaluation

    The huge design space to develop the hardware/software infrastructure of MPSoCs (Multi-Processor System-on-Chip), or to evaluate the performance of applications requires frameworks able to generate and to simulate the MPSoC. The design of MPSoCs is a complex task. From the designer side point of view, a new feature inserted into...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2012

    Proposal and Evaluation of a Task Migration Protocol for NoC-Based MPSoCs

    Task migration is a well-known strategy adopted in distributed systems for load balancing. But the adoption of such strategy in NoC-based MPSoC is scarce in the literature. This paper proposes a complete task migration protocol for NoC-based MPSoCs. The migration transfers the task code, data and context to another PE....

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2009

    Evaluation of Static and Dynamic Task Mapping Algorithms in NoC-Based MPSoCs

    Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    A Monitored NoC with Runtime Path Adaptation

    Network-on-Chips (NoCs) are already a common choice of communication infrastructure for complex System-on-Chips (SoCs) containing a large number of processing resources and with critical communication requirements. A NoC provides several advantages, such as higher scalability, efficient energy management, higher bandwidth and lower average latency, when compared to bus-based systems. Experiments...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Mar 2013

    ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design

    The asynchronous circuit design paradigm provides a practical solution for several challenges and constraints of current and future technologies to build integrated circuits and systems. However, there is little electronic design automation support for this paradigm. This work presents a standard cell library designed to support a semi-custom approach in...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2007

    Reducing the Power Consumption in Networks-on-Chip Through Data Coding Schemes

    In this paper, the authors investigate the reduction of power consumption in Network-on-Chips (NoCs) through the reduction of transition activity using data coding schemes developed for bus-based systems and propose a new coding scheme suitable for NoC-based systems. The estimation of the NoC power consumption was performed with basis on...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2011

    Exploring Heterogeneous NoC-Based MPSoCs: From FPGA to High-Level Modeling

    In this paper, the authors propose a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. They propose a solution that uses a unified model-based framework, which is calibrated according to...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2008

    Buffer Sizing for Multimedia Flows in Packet-Switching NoCs

    Network-on-Chips (NoCs) have been investigated in the last few years as a promising alternative to bus-based and point-to-point architectures to interconnect Intellectual Property cores (IPs) in System-on-Chips (SoCs). NoCs allow simultaneous transactions between several pairs of cores (parallelism) and the connection of new IPs does not imply redesigning the communication...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jul 2010

    Hermes-A - An Asynchronous NoC Router with Distributed Routing

    Interest in asynchronous circuits has increased due the growing limitations faced during the design of synchronous System-on-Chip (SoC) circuits, which often result in over constrained design and operation. However, asynchronous Computer Aided Design (CAD) tools still have to undergo a long evolutionary path before being accepted by most designers. The...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jun 2012

    Scheduling MapReduce Jobs in HPC Clusters

    MapReduce (MR) has become a de facto standard for large-scale data analysis. Moreover, it has also attracted the attention of the HPC community due to its simplicity, efficiency and highly scalable parallel model. However, MR implementations present some issues that may complicate its execution in existing HPC clusters, especially concerning...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Oct 2012

    Evaluation of Adaptive Management Techniques in NoC-Based MPSoCs

    Self-adaptation capability is as a key feature to meet runtime application requirements in dynamic systems such as NoC-based MPSoCs. In this paper, the authors present an evaluation of adaptive management techniques combined with task monitoring, which is able to change at runtime the communication priority, the tasks scheduling priority and...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2013

    Achieving QoS in NoC-Based MPSoCs Through Dynamic Frequency Scaling

    The management of Quality-of-Service (QoS) constraints in NoC-based MPSoCs, with dozens of tasks running simultaneously, is still a challenge. Techniques applied at design or run-time to address this issue adopts different QoS metrics. Designers include in their systems monitoring techniques, adapting at run-time the QoS parameters to cope with the...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2013

    Determining the Test Sources/Sinks for NoC TAMs

    Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Sep 2009

    Investigating Runtime Task Mapping for NoC-Based Multiprocessor SoCs

    Multi-Processor System-on-Chips (MPSoCs) are a trend in VLSI design, since they minimize the design crisis configured by the gap between the silicon technology and the actual SoC design capacity. An important issue in MPSoCs is task mapping. Applications running in MPSoCs execute a varying number of tasks simultaneously, where each...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Jan 2014

    Runtime Fault Recovery Protocol for NoC-Based MPSoCs

    The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This paper presents a novel fault-tolerant communication protocol that...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // Dec 2013

    Evaluating the Trade-Off Between DVFS Energy-Savings and Virtual Networks Performance

    Data centers usually employ virtualization techniques coupled with other techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), in order to reduce overall energy consumption. However, changes in processor frequency may impact the network performance, specifically in metrics such as throughput and jitter. This paper evaluates the trade-off between changes...

    Provided By Pontifical Catholic University of Rio de Janeiro

  • White Papers // May 2006

    Reconfigurable Systems Enabled by a Network-on-Chip

    A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for general-purpose tasks. Flexibility is the key feature of processors, since it is easy to modify their tasks behavior at runtime. However, most current SoCs have no capability to modify the hardware behavior or structure...

    Provided By Pontifical Catholic University of Rio de Janeiro