University of Calgary

Displaying 1-40 of 549 results

  • White Papers // Jan 2015

    Extended Interface Grammars for Automated Stub Generation

    An important challenge in software verification is the ability to verify different software components in isolation. Achieving modularity in software verification requires development of innovative interface specification languages. In this paper the authors focus on the idea of using grammars for specification of component interfaces. In earlier work, they investigated...

    Provided By University of Calgary

  • White Papers // Jan 2015

    Applying Infinite State Model Checking and Other Analysis Techniques to Tabular Requirements Specifications of Safety-Critical Systems

    Although it is most often applied to finite state models, in recent years, symbolic model checking has been extended to infinite state models using symbolic representations that encode infinite sets. This paper investigates the application of an infinite state symbolic model checker called Action Language Verifier (ALV) to formal requirements...

    Provided By University of Calgary

  • White Papers // Jan 2015

    Modular Verification of Synchronization with Reentrant Locks

    The authors present a modular approach for verification of synchronization behavior in concurrent programs that use reentrant locks. Their approach decouples the verification of the lock implementation from the verification of the threads that use the lock. This decoupling is achieved using lock interfaces that characterize the allowable execution order...

    Provided By University of Calgary

  • White Papers // Jan 2015

    Computing Real Time Jobs in P2P Networks

    In this paper, the authors present a distributed computing framework designed to support higher quality of service and fault tolerance for processing deadline-driven tasks in a P2P environment. Their proposed strategy strives to build an open infrastructure that is accessible by ordinary users for both cycle donation and consumption. For...

    Provided By University of Calgary

  • White Papers // Jan 2015

    Analyzing Tabular Requirements Specifications Using Infinite State Model Checking

    In this paper, the authors investigate the application of infinite state model checking to the formal analysis of requirements specifications in the SCR (Software Cost Reduction) tabular notation using Action Language Verifier (ALV). After reviewing the SCR method and tools and the Action Language, experimental results are presented of formally...

    Provided By University of Calgary

  • White Papers // Jan 2015

    Analyzing Conversations: Realizability, Synchronizability, and Verification

    Conversations provide an intuitive and simple model for analyzing interactions among composite web services. A conversation is the global sequence of messages exchanged among the peers participating to a composite web service. Interactions in a composite web service can be analyzed by investigating the temporal properties of its conversations. Conversations...

    Provided By University of Calgary

  • White Papers // Nov 2014

    To Go or Not to Go: On Energy-aware and Communication-aware Robotic Operation

    The authors consider the scenario where a mobile robot needs to visit a number of Points Of Interest (POIs) in a workspace, gather their generated bits of information, and successfully transmit them to a remote station, while operating in a realistic communication environment, minimizing its total energy consumption (including both...

    Provided By University of Calgary

  • White Papers // Sep 2014

    CloudTracker: Using Execution Provenance to Optimize the Cost of Cloud Use

    In this paper, the authors investigate tools that enable dollar cost optimization of scientific simulations using commercial clouds. They present a framework, called CloudTracker that transparently records information from a simulation that is executed in a commercial cloud so that it may be \"Replayed\" exactly to reproduce its results. Using...

    Provided By University of Calgary

  • White Papers // Jul 2014

    Automata-Based Symbolic String Analysis for Vulnerability Detection

    Verifying string manipulating programs is a crucial problem in computer security. String operations are used extensively within web applications to manipulate user input, and their erroneous use is the most common cause of security vulnerabilities in web applications. The authors present an automata-based approach for symbolic analysis of string manipulating...

    Provided By University of Calgary

  • White Papers // Jul 2014

    BareCloud: Bare-metal Analysis-based Evasive Malware Detection

    The volume and the sophistication of malware are continuously increasing and evolving. Automated dynamic malware analysis is a widely-adopted approach for detecting malicious software. However, many recent malware samples try to evade detection by identifying the presence of the analysis environment itself, and refraining from performing malicious actions. Because of...

    Provided By University of Calgary

  • White Papers // Jul 2014

    Hulk: Eliciting Malicious Behavior in Browser Extensions

    The authors present Hulk, a dynamic analysis system that detects malicious behavior in browser extensions by monitoring their execution and corresponding network activity. Hulk elicits malicious behavior in extensions in two ways. First, Hulk leverages HoneyPages, which are dynamic pages that adapt to an extension's expectations in web page structure...

    Provided By University of Calgary

  • White Papers // Jul 2014

    EmergeNet: Robust, Rapidly Deployable Cellular Networks

    Cellular phone networks are often paralyzed after a disaster, as damage to fixed infrastructure, loss of power, and increased demand degrade coverage and quality of service. To ensure disaster victims and first responders have access to reliable local and global communication, the authors propose EmergeNet, a portable, rapidly deployable, small...

    Provided By University of Calgary

  • White Papers // Jun 2014

    DRoP:DNS-based Router Positioning

    In this paper, the authors focus on geolocating Internet routers, using a methodology for extracting and decoding geography-related strings from fully qualified domain names (hostnames). They first compiled an extensive dictionary associating geographic strings (e.g., airport codes) with geophysical locations. They then searched a large set of router hostnames for...

    Provided By University of Calgary

  • White Papers // May 2014

    Empirically Characterizing Domain Abuse and the Revenue Impact of Blacklisting

    Using ground truth sales data for over 40K unlicensed prescription pharmaceuticals sites, the authors present an economic analysis of two aspects of domain abuse in the online counterfeit drug market. First, they characterize the nature of domains abused by affiliate spammers to monetize what is evidently an overwhelming demand for...

    Provided By University of Calgary

  • White Papers // May 2014

    Asymptotically Optimal Sequential Tests for Anomaly Detection: Switching with Memory

    Each anomalous process incurs a cost per unit time until its anomaly is identified and fixed. Different anomalous processes may incur different costs depending on their criticality to the system. Switching between processes and state declarations are allowed at all times, while decisions are based on all past observations and...

    Provided By University of Calgary

  • White Papers // May 2014

    Automatic and Portable Cloud Deployment for Scientific Simulations

    In this paper, the authors present CloudRunner, a framework that extracts arbitrary programs from a source code repository (e.g. GitHub), wraps them in a web service and tasking system, and deploys them over disparate cloud infrastructures and local clusters, automating their portability. In particular, CloudRunner automatically creates and configures virtual...

    Provided By University of Calgary

  • White Papers // May 2014

    Enhanced Lattice-Based Signatures on Reconfigurable Hardware

    The recent Bimodal LattIce Signature Scheme (BLISS) showed that lattice-based constructions have evolved to practical alternatives to RSA or ECC. Besides reasonably small signatures with 5600 bits for a 128-bit level of security, BLISS enables extremely fast signing and signature verification in software. However, due to the complex sampling of...

    Provided By University of Calgary

  • White Papers // May 2014

    A Sampling-Based Approach to Scalable Constraint Satisfaction in Linear Sampled-Data Systems - Part I: Computation

    Sampled-Data (SD) systems, which are composed of both discrete- and continuous-time components, are arguably one of the most common classes of cyber-physical systems in practice; most modern controllers are implemented on digital platforms while the plant dynamics that are being controlled evolve continuously in time. As with all cyber-physical systems,...

    Provided By University of Calgary

  • White Papers // May 2014

    Scalable Fault-Tolerant Data Feeds in AsterixDB

    In this paper, the authors describe the support for data feed ingestion in AsterixDB, an open-source Big Data Management System (BDMS) that provides a platform for storage and analysis of large volumes of semi-structured data. Data feeds are a mechanism for having continuous data arrive into a BDMS from external...

    Provided By University of Calgary

  • White Papers // May 2014

    ReDHiP: Recalibrating Deep Hierarchy Prediction for Energy Efficiency

    Recent hardware trends point to increasingly deeper cache hierarchies. In such hierarchies, accesses that lookup and miss in every cache involve significant energy consumption and degraded performance. To mitigate these problems, in this paper the authors propose Recalibrating Deep Hierarchy Prediction (ReDHiP), an architectural mechanism that predicts Last-Level Cache (LLC)...

    Provided By University of Calgary

  • White Papers // Apr 2014

    Multi-Level Coded Caching

    Recent work has demonstrated that for content caching, joint design of storage and delivery can yield significant benefits over conventional caching approaches. This is based on storing content in the caches, so as to create coded-multicast opportunities even amongst users with different demands. Such a coded-caching scheme has been shown...

    Provided By University of Calgary

  • White Papers // Apr 2014

    Towards Automatically Estimating Porting Effort Between Web Service APIs

    In this paper, the authors describe a new methodology for automatically quantifying the relative work required for a programmer to port an application from one web API to another, i.e. \"Porting effort\". Their approach defines a simple language (based on Python) with which API developers specify the semantics of API...

    Provided By University of Calgary

  • White Papers // Apr 2014

    SELFISHMIGRATE: A Scalable Algorithm for Non-Clairvoyantly Scheduling Heterogeneous Processors

    Many computer architects believe that architectures consisting of heterogeneous processors will be the dominant architectural design in the future: simulation studies indicate that, for a given area and power budget, heterogeneous multiprocessors can offer an order of magnitude better performance for typical workloads. Looking at the consequences of Moore's Law...

    Provided By University of Calgary

  • White Papers // Mar 2014

    Lithography-Induced Limits to Scaling of Design Quality

    Quality and value of an IC product are functions of power, performance, area, cost and reliability. The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore's Law scaling of layout densities, the \"Realizable\" scaling in competitive products has for some years been significantly less. In this...

    Provided By University of Calgary

  • White Papers // Mar 2014

    VANET via Named Data Networking

    Recently manufactured vehicles are equipped with not only computation powers but also a variety of wireless communication interfaces such as 3G/LTE, WiMAX, Wi-Fi, IEEE 1901 (power line communication), and 802.11p (DSRC/WAVE). In this paper, the authors apply the named data networking, a newly proposed Internet architecture, to networking vehicles on...

    Provided By University of Calgary

  • White Papers // Mar 2014

    Circuit Switching Under the Radar with REACToR

    The potential advantages of optics at high link speeds have led to significant interest in deploying optical switching technology in data-center networks. Initial efforts have focused on hybrid approaches that rely on millisecond-scale circuit switching in the core of the network, while maintaining the flexibility of electrical packet switching at...

    Provided By University of Calgary

  • White Papers // Feb 2014

    SENIC: Scalable NIC for End-Host Rate Limiting

    Rate limiting is an important primitive for managing server network resources. Unfortunately, software-based rate limiting suffers from limited accuracy and high CPU overhead, and modern NICs only support a handful of rate limiters. The authors present SENIC, a NIC design that can natively support 10s of thousands of rate limiters...

    Provided By University of Calgary

  • White Papers // Feb 2014

    SAFEDISPATCH: Securing C++ Virtual Calls from Memory Corruption Attacks

    Several defenses have increased the cost of traditional, low-level attacks that corrupt control data, e.g. return addresses saved on the stack, to compromise program execution. In response, creative adversaries have begun circumventing these defenses by exploiting programming errors to manipulate pointers to virtual tables, or vtables, of C++ objects. These...

    Provided By University of Calgary

  • White Papers // Feb 2014

    The Melbourne Shuffle: Improving Oblivious Storage in the Cloud

    The authors present a simple, efficient, and secure data-oblivious randomized shuffle algorithm. This is the first secure data-oblivious shuffle that is not based on sorting. Their method can be used to improve previous oblivious storage solutions for network-based outsourcing of data. One of the unmistakable recent trends in networked computation...

    Provided By University of Calgary

  • White Papers // Feb 2014

    Optimal Reliability-Constrained Overdrive Frequency Selection In Multicore Systems

    In leading-edge process technologies, reliability is a first-class constraint for both IC design and system operation. For multicore systems, reliability affects task scheduling decisions since it constrains both performance and throughput. Previous works on reliability-constrained task scheduling have two basic limitations: either they cannot guarantee lifetime (e.g., that the chip...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Automated Test Generation from Vulnerability Signatures

    Web applications need to validate and sanitize user inputs in order to avoid attacks such as Cross Site Scripting (XSS) and SQL injection. Writing string manipulation code for input validation and sanitization is an error-prone process leading to many vulnerabilities in real-world web applications. Automata-based static string analysis techniques can...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Cloud Platform Support for API Governance

    As scalable information technology evolves to a more cloud-like model, digital assets (code, data and software environments) increasingly require duration as web-accessible services. \"Service-izing\" digital assets consist of encapsulating assets in software that exposes them to web and mobile applications via well-defined yet flexible, network accessible, Application Programming Interfaces (APIs)....

    Provided By University of Calgary

  • White Papers // Jan 2014

    NOLO : A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation

    Useful skew is a well-known design technique that adjusts clock sink latencies to improve performance and/or robustness of high-performance IC designs. Current design methodologies apply useful skew after the netlist has been synthesized (e.g., with a uniform skew or clock uncertainty assumption on all flops), and after placement has been...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Timing Margin Recovery with Flexible Flip-Flop Timing Model

    In timing signoff for leading-edge SOCs, even few-picosecond timing violations will not only increase design turnaround time, but also degrade design quality (e.g., through power increase from insertion of extra buffers). Conventional flip-flop timing models have fixed values of setup/hold times and clock-to-q (c2q) delay, with some advanced \"Setup-Hold Pessimism...

    Provided By University of Calgary

  • White Papers // Jan 2014

    A GALS Many-Core Heterogeneous DSP Platform with Source-Synchronous On-Chip Interconnection Network

    In this paper, the authors present a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedded applications that have a high degree of task-level parallelism among computational kernels. The test chip was fabricated in 65nm CMOS consisting of 164 simple...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Modeling and Detecting Control Errors in Microprocessors

    Hardware verification has long been handicapped by the absence of good high-level design error models. To be useful for design validation, error models should satisfy three requirements: tests (simulation vectors) that cover the modeled errors should also provide very high coverage of actual design errors; the modeled errors should be...

    Provided By University of Calgary

  • White Papers // Jan 2014

    High Throughput and Energy Efficient LDPC Decoders Using Multi-Split-Row Threshold Method

    Low Density Parity Check (LDPC) codes have received significant attention due to their superior error correction performance, and have been considered by emerging communication standards such as 10 Gigabit Ethernet (10GBASE-T), Digital Video Broadcasting (DVBS2), WiMAX (802.16e), Wi-Fi (802.11n) and WPANs (802.15.3c). Due to the codes' inherently irregular and global...

    Provided By University of Calgary

  • White Papers // Jan 2014

    On Computation and Resource Management in Networked Embedded Systems

    In this paper, the authors present the idea of managing the comprising computations of an application performed by an embedded networked system. An efficient algorithm for exploiting the timing slack of building blocks of the application is proposed. The slack of blocks can be utilized by replacing them with slower...

    Provided By University of Calgary

  • White Papers // Jan 2014

    A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors

    The Globally Asynchronous Locally Synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing global clocking circuits at high clock frequencies in the GHz range. In this paper, the authors present a high-speed interconnect network for a GALS multiprocessing system composed...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Dynamic Information Flow Tracking on Multicores

    Dynamic Information Flow Tracking (DIFT) is a promising technique for detecting software attacks. Due to the computationally intensive nature of the technique, prior efficient implementations rely on specialized hardware support whose only purpose is to enable DIFT. Alternatively, prior software implementations are either too slow resulting in execution time increases...

    Provided By University of Calgary

  • White Papers // Jan 2012

    DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

    DCAF is a directly connected arbitration free photonic crossbar that is realized by taking advantage of multiple photonic layers connected with photonic vias. In order to evaluate DCAF the authors developed a detailed implementation model for the network and analyzed the power and performance on a variety of benchmarks, including...

    Provided By University of Calgary

  • White Papers // May 2013

    Toward Quantifying the IC Design Value of Interconnect Technology Improvements

    As technology scales, wire delay due to interconnect Resistance (R) and Capacitance (C) is increasing. Thus, improvement of middle-of-line and Back-End-Of-Line (BEOL) materials and process technology (e.g., to achieve reduced barrier material thickness or dielectric permittivity) has always been a key goal in the technology roadmap. However, to date there...

    Provided By University of Calgary

  • White Papers // Feb 2007

    Data Reuse Driven Memory and Network-on-Chip Co-Synthesis

    Network-on-Chips (NoCs) present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a significant source of energy consumption and many attempts at energy efficient NoC synthesis have been proposed. However, in addition to the communication subsystem, the memory subsystem is an...

    Provided By University of Calgary

  • White Papers // Nov 2009

    Slack Redistribution for Graceful Degradation Under Voltage Overscaling

    Modern digital IC designs have a critical operating point, or \"Wall of slack\", that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage...

    Provided By University of Calgary

  • White Papers // Nov 2009

    Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs

    Current processor designs have a critical operating point that sets a hard limit on voltage scaling. Any scaling beyond the critical voltage results in exceeding the maximum allowable error rate, i.e., there are more timing errors than can be effectively and gainfully detected or corrected by an error-tolerance mechanism. This...

    Provided By University of Calgary

  • White Papers // Mar 2006

    Firm Real-Time Processing in an Integrated Real-Time System

    The authors explore the integration of firm real-time processing - where processing completed after its deadline has no value but some jobs may be terminated or skipped - into an integrated real-time system managing hard, soft, and non-real-time processes. They show that it is feasible to add firm real-time processing...

    Provided By University of Calgary

  • White Papers // Feb 2012

    Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems

    Integrating optical interconnects into the next generation multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughput, latency, and power efficiency of electrical interconnects. Optical interconnects also allow the performance growth of inter-core connectivity to keep pace with the growth of the cores' processing ability. However,...

    Provided By University of Calgary

  • White Papers // Oct 2012

    Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip

    Recent advances in nano-photonic fabrication have made the optical network-on-chip an attractive interconnect option for next-generation multi-/many-core systems, providing high bandwidth and power efficiency. Both post-fabrication and runtime calibration of the optical components (ring resonators) are essential to building a robust optical communication system, as they are highly sensitive to...

    Provided By University of Calgary

  • White Papers // Jun 2010

    An Energy-Efficient Parallel H.264/AVC Baseline Encoder on a Fine-Grained Many-Core System

    The emerging many-core architecture provides a flexible solution for the rapid evolving multimedia applications demanding both high performance and high energy-efficiency. However, developing parallel multimedia applications that can efficiently harness and utilize manycore architectures is the key challenge for scalable computing. The authors contribute to this challenge by presenting a...

    Provided By University of Calgary

  • White Papers // Feb 2009

    The Design of a Reconfigurable Continuous-Flow Mixed-Radix FFT Processor

    The design of a highly configurable Continuous Flow Mixed-Radix (CFMR) Fast Fourier Transform (FFT) processor is presented. It computes fixed-point complex FFTs and Inverse FFTs (IFFTs), and utilizes a flexible addressing scheme to enable runtime configuration of the FFT length from 16-points to 4096- points. A configurable Block Floating Point...

    Provided By University of Calgary

  • White Papers // Oct 2012

    A Hexagonal Shaped Processor and Interconnect Topology for Tightly-Tiled Many-Core Architecture

    Two-dimensional meshes are the most commonly used Network-on-Chip (NoC) topology for on-chip communication in many-core processor arrays due to their low complexity and excellent match to rectangular processor tiles. However, 2D meshes may incur local traffic congestion for applications with significant levels of traffic with non-neighboring cores, resulting in long...

    Provided By University of Calgary

  • White Papers // Oct 2012

    Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array

    Data centers require significant and growing amounts of power to operate, and with increasing numbers of data centers worldwide, power consumption for enterprise workloads is a significant concern. Sorting is a key computational kernel in large database systems, and the development of energy efficient sorting capabilities would therefore significantly reduce...

    Provided By University of Calgary

  • White Papers // Apr 2008

    A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling

    Recent chips containing a large number of programmable processing elements are proving to be efficient and flexible platforms for computing DSP and multimedia applications. Several significant remaining challenges include: reducing power dissipation of processors when lightly loaded or unused, achieving low energy while maintaining performance on common demanding tasks such...

    Provided By University of Calgary

  • White Papers // Jan 2014

    A GALS Many-Core Heterogeneous DSP Platform with Source-Synchronous On-Chip Interconnection Network

    In this paper, the authors present a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedded applications that have a high degree of task-level parallelism among computational kernels. The test chip was fabricated in 65nm CMOS consisting of 164 simple...

    Provided By University of Calgary

  • White Papers // Jun 2012

    Energy-Efficient AES Ciphers on a Fine-Grained Many-Core System

    By exploring different granularities of data-level and task-level parallelism, The authors propose 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only 6 cores for offline key expansion and 8 cores for online key...

    Provided By University of Calgary

  • White Papers // May 2007

    High-Throughput LDPC Decoders Using A Multiple Split-Row Method

    Low density parity check codes first introduced by the researcher have recently received significant attention due to their significant error correction performance and their inherent parallelizable decoder architectures. Many recent communication standards such as 10 Gigabit Ethernet (10GBASET) and Digital Video Broadcasting (DVB-S2) have adopted LDPC codes. The authors propose...

    Provided By University of Calgary

  • White Papers // Nov 2011

    A High-Performance Area-Efficient AES Cipher on a Many-Core Platform

    In this paper, the authors present the design and software implementation of a high-performance area-efficient Advanced Encryption Standard (AES) cipher on a many-core platform. A preliminary cipher design is partitioned and mapped to an array of 70 small processors, and offers a throughput of 16.625 clock cycles per byte. The...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Modeling and Detecting Control Errors in Microprocessors

    Hardware verification has long been handicapped by the absence of good high-level design error models. To be useful for design validation, error models should satisfy three requirements: tests (simulation vectors) that cover the modeled errors should also provide very high coverage of actual design errors; the modeled errors should be...

    Provided By University of Calgary

  • White Papers // Jun 2011

    Design of Bufferless On-Chip Routers Providing In-Order Packet Delivery

    Previous bufferless router designs require dropping and retransmitting packets or deflect them each time a network channel get conflicted. These approaches, unfortunately, make data packets and even their flits arrive at destinations out-of-order. In this paper, the authors present a new bufferless router architecture that provides in-order packet delivery. The...

    Provided By University of Calgary

  • White Papers // Jan 2014

    High Throughput and Energy Efficient LDPC Decoders Using Multi-Split-Row Threshold Method

    Low Density Parity Check (LDPC) codes have received significant attention due to their superior error correction performance, and have been considered by emerging communication standards such as 10 Gigabit Ethernet (10GBASE-T), Digital Video Broadcasting (DVBS2), WiMAX (802.16e), Wi-Fi (802.11n) and WPANs (802.15.3c). Due to the codes' inherently irregular and global...

    Provided By University of Calgary

  • White Papers // Jan 2014

    On Computation and Resource Management in Networked Embedded Systems

    In this paper, the authors present the idea of managing the comprising computations of an application performed by an embedded networked system. An efficient algorithm for exploiting the timing slack of building blocks of the application is proposed. The slack of blocks can be utilized by replacing them with slower...

    Provided By University of Calgary

  • White Papers // Mar 2007

    Circuit Profiling Mechanisms for High-Level ATPG

    The authors' Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, they need to enable MVP's ATPG to learn important details of the circuit under validation as a means to explore critical new circuit scenarios. In this paper, they...

    Provided By University of Calgary

  • White Papers // Feb 2009

    Multi-Split-Row Threshold Decoding Implementations for LDPC Codes

    The recently introduced split-row threshold algorithm significantly improves the error performance when compared to the non-threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The multi-split-row threshold decoding algorithm presented in this paper enables further reductions in routing complexity for greater throughput and smaller circuit area implementations....

    Provided By University of Calgary

  • White Papers // Jan 2014

    A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors

    The Globally Asynchronous Locally Synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing global clocking circuits at high clock frequencies in the GHz range. In this paper, the authors present a high-speed interconnect network for a GALS multiprocessing system composed...

    Provided By University of Calgary

  • White Papers // Jul 2012

    NoCTweak: A Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip

    As the number of Processing Elements (PE) on a single chip increases with each generation of CMOS technology, Network-on-Chip (NoC) has become a de-facto communication fabric for this PEs. Due to high design and test costs for real many-core chips, simulators which allow exploring the best design options for a...

    Provided By University of Calgary

  • White Papers // Mar 2008

    Performance Comparison of SRAM Cells Implemented in 6, 7 and 8-Transistor Cell Topologies

    Cell stability and area are among the major concerns in SRAM cell designs. This paper compares the performance of three SRAM cell topologies, which include the conventional 6T-cell and the recently published 7T and 8T-cell implementations. In particular, the Static-Noise-Margin (SNM) of each cell design is examined. Even though 7T...

    Provided By University of Calgary

  • White Papers // Jan 2014

    Dynamic Information Flow Tracking on Multicores

    Dynamic Information Flow Tracking (DIFT) is a promising technique for detecting software attacks. Due to the computationally intensive nature of the technique, prior efficient implementations rely on specialized hardware support whose only purpose is to enable DIFT. Alternatively, prior software implementations are either too slow resulting in execution time increases...

    Provided By University of Calgary

  • White Papers // Dec 2006

    A Cross-Layer Cross-Overlay Architecture for Proactive Adaptive Processing in Mesh Networks

    The dynamic characteristics of wireless mesh network environments make delay-sensitive multimedia applications processing in such networks a very challenging task. Cross-layer optimizations are commonly designed to ensure that application requirements are met. Improved timeliness of delivery and precision of information as acquired by a decision-entity can help in effective management...

    Provided By University of Calgary

  • White Papers // Jan 2009

    Noncespaces: Using Randomization to Enforce Information Flow Tracking and Thwart Cross-Site Scripting Attacks

    Cross-Site Scripting (XSS) vulnerabilities are among the most common and serious web application vulnerabilities. Eliminating XSS is challenging because it is difficult for web applications to sanitize all user inputs appropriately. The authors present Noncespaces, a technique that enables web clients to distinguish between trusted and untrusted content to prevent...

    Provided By University of Calgary

  • White Papers // Aug 2010

    CapAuth: A Capability-Based Handover Scheme

    Existing handover schemes in wireless LANs, 3G/4G networks, and femtocells rely upon protocols involving centralized authentication servers and one or more access points. These protocols are invariably complex and use extensive signaling on the wireless backhaul since they aim to be efficient (minimal handover latency) without sacrificing robustness. However, the...

    Provided By University of Calgary

  • White Papers // Apr 2012

    I-ARM-Droid: A Rewriting Framework for In-App Reference Monitors for Android Applications

    Mobile applications are a major force behind the explosive growth of mobile devices. While they greatly extend the functionality of mobile devices, they also raise security and privacy concerns, especially when they have not gone through a rigorous review process. To protect users from untrusted and potentially malicious applications, the...

    Provided By University of Calgary

  • White Papers // Jun 2013

    Quantifying the Effects of Removing Permissions from Android Applications

    With the growing popularity of android smart phones, it is increasingly important to ensure the security of sensitive user information. A recent study found that approximately 26% of android applications in Google play can access personal data, such as contacts and email, and 42 percent, GPS location data. While android...

    Provided By University of Calgary

  • White Papers // Feb 2013

    Cloud Template, a Big Data Solution

    Today cloud computing has become as a new concept for hosting and delivering different services over the Internet for big data solutions. Cloud computing is attractive to different business owners of both small and enterprise as it eliminates the requirement for users to plan ahead for provisioning, and allows enterprises...

    Provided By University of Calgary

  • White Papers // Sep 2012

    A Static Binary Instrumentation Threading Model for Fast Memory Trace Collection

    As hardware vendors push for higher levels of concurrency in multicore and manycore chips, the HPC software running on that hardware must increasingly utilize sophisticated models of parallelization, including interprocess message passing via MPI or SHMEM, intraprocess data sharing via threading models such as pthreads and OpenMP, and combinations of...

    Provided By University of Calgary

  • White Papers // Jan 2011

    Error-Correcting Codes for Flash Coding

    Flash memory is a non-volatile computer storage device which consists of blocks of cells. While increasing the voltage level of a single cell is fast and simple, reducing the level of a cell requires the erasing of the entire block containing the cell. Since block-erasures are costly, traditional flash coding...

    Provided By University of Calgary

  • White Papers // Dec 2010

    Reliably Erasing Data From Flash-Based Solid State Drives

    Reliably erasing data from storage media (sanitizing the media) is a critical component of secure data management. While sanitizing entire disks and individual files is well-understood for hard drives, flash-based solid state disks have a very different internal architecture, so it is unclear whether hard drive techniques will work for...

    Provided By University of Calgary

  • White Papers // Jun 2011

    Onyx: A Protoype Phase Change Memory Storage Array

    Storage devices based on non-volatile, solid-state memories are rewriting the rules governing the relationship between storage devices and the rest of computer systems. Flash-based SSDs are in the vanguard of this change, but faster, more reliable, and less idiosyncratic technologies are on the horizon. Of these advanced nonvolatile memories, Phase-Change...

    Provided By University of Calgary

  • White Papers // Apr 2013

    Minerva: Accelerating Data Analysis in Next-Generation SSDs

    Emerging Non-Volatile Memory (NVM) technologies have DRAM-like latency with storage-like density, offering unique capability to analyze large data sets significantly faster than flash or disk storage. However, the hybrid nature of these NVM technologies such as Phase-Change Memory (PCM) makes it difficult to use them to best advantage in the...

    Provided By University of Calgary

  • White Papers // Apr 2013

    Latency-Optimized Networks for Clustering FPGAs

    The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support random requests to unstructured (e.g., logs) and semi-structured (e.g., large graph and XML) data sets. To explore the suitability of FPGAs for these computations, the authors...

    Provided By University of Calgary

  • White Papers // Mar 2011

    Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

    In this paper the authors describe an architecture and FPGA synthesis tool-chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is...

    Provided By University of Calgary