University of Economics, Prague

Displaying 1-40 of 69 results

  • White Papers // Jul 2014

    Business Rule Learning with Interactive Selection of Association Rules

    Today, there is an increasing demand for Decision Support Systems (DSS). The penetration of DSS solutions to many domains is stifled by the fact that building a DSS requires a significant amount of time from users, who need to be not only domain experts, but also skilled knowledge engineers. This...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    TSO-CC: Consistency Directed Cache Coherence for TSO

    Traditional directory coherence protocols are designed for the strictest consistency model, Sequential Consistency (SC). When they are used for Chip Multi-Processors (CMPs) that support relaxed memory consistency models, such protocols turn out to be unnecessarily strict. Usually this comes at the cost of scalability, which poses a problem with increasing...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    The Design and Performance of a Conflict-Avoiding Cache

    High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. In this paper, the authors investigate the...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    High Speed CPU Simulation Using JIT Binary Translation

    Instruction set simulators is indispensable tools for exploring the design-space of innovative processor architectures, for processor verification, and for software development. Traditional interpretive simulators are too slow to cope with the increasing complexity of embedded processors now being deployed in many high performance systems. High speed emulation techniques based on...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    Tradeoffs in XML Database Compression

    Large XML data les, or XML databases, are now a common way to distribute scientific and bibliographic data and storing such data efficiently is an important concern. A number of approaches to XML compression have been proposed in the last five years. The most competitive approaches employ one or more...

    Provided By University of Economics, Prague

  • White Papers // Oct 2013

    Distributed Coordinate Descent Method for Learning with Big Data

    In this paper, the authors develop and analyze Hydra: HYbriD cooRdinAte descent method for solving loss minimization problems with big data. They initially partition the coordinates (features) and assign each partition to a different node of a cluster. At every iteration, each node picks a random subset of the coordinates...

    Provided By University of Economics, Prague

  • White Papers // Sep 2013

    Aligned Scheduling: Cache-efficient Instruction Scheduling for VLIW Processors

    The performance of statically scheduled VLIW processors is highly sensitive to the instruction scheduling performed by the compiler. In this paper, the authors identify a major deficiency in existing instruction scheduling for VLIW processors. Unlike most dynamically scheduled processors, a VLIW processor with no load-use hardware interlocks will completely stall...

    Provided By University of Economics, Prague

  • White Papers // Sep 2013

    OpenCL Task Partitioning in the Presence of GPU Contention

    Heterogeneous multi- and many-core systems are increasingly prevalent in the desktop and mobile domains. On these systems it is common for programs to compete with co-running programs for resources. While multi-task scheduling for CPUs is a well-studied area, how to partitioning and map computing tasks onto the heterogeneous system in...

    Provided By University of Economics, Prague

  • White Papers // Aug 2013

    Geometric Methods of Information Storage and Retrieval in Sensor Networks

    Sensor networks collect data from their environment. Locations of the sensors are important attributes of that information and provide a context to understand, and use sensor data. In this paper, the authors will discuss geometric ideas to organize sensor data using their locations. They will consider distributed methods for managing...

    Provided By University of Economics, Prague

  • White Papers // Jul 2013

    CAeSaR: Unified Cluster-Assignment Scheduling and Communication Reuse for Clustered VLIW Processors

    Clustered architectures have been proposed as a solution to the scalability problem of wide ILP processors. VLIW architectures, being wide-issue by design, benefit significantly from clustering. Such architectures, being both statically scheduled and clustered, require specialized code generation techniques, as they require explicit Inter-Cluster Copy instructions (ICCs) be scheduled in...

    Provided By University of Economics, Prague

  • White Papers // Jul 2013

    A Polynomial-Time Approximation Scheme for Fault-Tolerant Distributed Storage

    Many applications involve designing a system that will perform well in an uncertain environment. Sources of uncertainty include (for example) the demand when the authors are designing a server, the congestion when they are designing a routing protocol, and the failure of the system's own components when they are designing...

    Provided By University of Economics, Prague

  • White Papers // May 2013

    CloudMirror: Application-Aware Bandwidth Reservations in the Cloud

    Cloud computing providers today do not offer guarantees for the network bandwidth available in the cloud, preventing tenants from running their applications predictably. To provide guarantees, several recent research proposals offer tenants a virtual cluster abstraction, emulating physical networks. Whereas offering dedicated virtual network abstractions is a significant step in...

    Provided By University of Economics, Prague

  • White Papers // Mar 2013

    V-BOINC: The Virtualization of BOINC

    The Berkeley Open Infrastructure for Network Computing (BOINC) is an open source client-server middleware system created to allow projects with large computational requirements, usually set in the scientific domain, to utilize a technically unlimited number of volunteer machines distributed over large physical distances. However, various problems exist deploying applications over...

    Provided By University of Economics, Prague

  • White Papers // Feb 2013

    CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

    Aggressive silicon process scaling over the last years has made transistors faster and less power consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors. In this...

    Provided By University of Economics, Prague

  • White Papers // Jan 2013

    Word Storms: Multiples of Word Clouds for Visual Comparison of Documents

    Word clouds are a popular tool for visualizing documents, but they are not a good tool for comparing documents, because identical words are not presented consistently across different clouds. The authors introduce the concept of word storms, a visualization tool for analyzing corpora of documents. A word storm is a...

    Provided By University of Economics, Prague

  • White Papers // Jan 2013

    Low-Complexity Encoding of LDPC Codes: A New Algorithm and its Performance

    A new technique for efficient encoding of LDPC codes based on the known concept of Approximate Lower Triangulation (ALT) is introduced. The greedy permutation algorithm is presented to transform parity-check matrices into an Approximate Lower Triangular (ALT) form with minimum "Gap". A large girth, which is known to guarantee good...

    Provided By University of Economics, Prague

  • White Papers // Jan 2013

    The SME Co-Operation Framework: A Multi-Method Secondary Research Approach to SME Collaboration

    This paper presents the SME co-operation framework, a model created to analyze the field of SME collaboration and to understand how small businesses cooperate. The constructs of this study are based on previous research on inter-firm co-operation, which permits to cross-validate results from different studies, combine their findings and to...

    Provided By University of Economics, Prague

  • White Papers // Dec 2012

    Position Paper: Weak Heterogeneity as a Way of Adapting Multicores to Real Workloads

    There is a growing consensus that heterogeneous multicores are the future of CPUs. These processors would be composed of cores that are specifically adapted or tuned to particular types of applications and use cases, thereby increasing performance. The move from homogeneous to heterogeneous multicores causes the design space to explode,...

    Provided By University of Economics, Prague

  • White Papers // Dec 2012

    Parallel Coordinate Descent Methods for Big Data Optimization

    In this paper, the authors show that randomized (block) coordinate descent methods can be accelerated by parallelization when applied to the problem of minimizing the sum of a partially separable smooth convex function and a simple separable convex function. The theoretical speedup, as compared to the serial method, and referring...

    Provided By University of Economics, Prague

  • White Papers // Oct 2012

    Enterprise Risk Management and Budgetary Control: A Management Challenge

    Enterprise risk management has been increasingly claimed as a tool for improving the capability of companies in predicting and managing risks, enhancing planning and the achievement of their goals. This research argues that the managerial role of ERM and its link with budgeting is both a strategic and a management...

    Provided By University of Economics, Prague

  • White Papers // Aug 2012

    UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

    Clustered VLIW processors are scalable wide-issue statically scheduled processors. Their design is based on physically partitioning the otherwise shared hardware resources, a design which leads to both high performance and low energy consumption. In traditional clustered VLIW processors, all clusters operate at the same frequency. Heterogeneous clustered VLIW processors however,...

    Provided By University of Economics, Prague

  • White Papers // Aug 2012

    Mixed-Mode Implementation of PETSc for Scalable Linear Algebra on Multi-Core Processors

    With multi-core processors a ubiquitous building block of modern supercomputers, it is now past time to enable applications to embrace these developments in processor design. To achieve exascale performance, applications will need ways of exploiting the new levels of parallelism that are exposed in modern high-performance computers. A typical approach...

    Provided By University of Economics, Prague

  • White Papers // Aug 2012

    The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

    The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and...

    Provided By University of Economics, Prague

  • White Papers // Jul 2012

    Inferring Data Currency and Consistency for Conflict Resolution

    In this paper, the authors introduce a new approach for conflict resolution: given a set of tuples pertaining to the same entity, it is to identify a single tuple in which each attribute has the latest and consistent value in the set. This problem is important in data integration, data...

    Provided By University of Economics, Prague

  • White Papers // Jul 2012

    Energy Efficient Resource Allocation in OFDMA Networks Using Ant-Colony Optimization

    A novel technique for jointly allocating sub-carriers, Modulation and Coding Scheme (MCS) and transmit power in an Orthogonal Frequency Division Multiple Access (OFDMA) cellular network using ant-colony optimization technique is proposed. Different combinations of user indices, MCS indices and subcarrier indices form the nodes in the graph. Each possible assignment...

    Provided By University of Economics, Prague

  • White Papers // Jun 2012

    Evaluating Speech Intelligibility Enhancement for HMM-Based Synthetic Speech in Noise

    It is possible to increase the intelligibility of speech in noise by enhancing the clean speech signal. In this paper, the authors demonstrate the effects of modifying the spectral envelope of synthetic speech according to the environmental noise. To achieve this, they modify Mel cepstral coefficients according to an intelligibility...

    Provided By University of Economics, Prague

  • White Papers // May 2012

    Robust SLNR Downlink Beamforming Based on Markov's Inequality

    This paper considers the Multi-User Multiple-Input and Multiple-Output (MU-MIMO) downlink system where each user is equipped with multiple receive antennas. Due to the inevitable channel imperfection, the system performance may degrade significantly. A robust Signal-to-Leakage-and-Noise Ratio (SLNR)-based beamforming is developed to provide robustness against channel uncertainties, which maximizes the expectation...

    Provided By University of Economics, Prague

  • White Papers // May 2012

    Performance Evaluation and Energy Efficiency of Random Network Coding in LTE-Advanced

    In this paper, the authors propose integration of Random Network Coding (R-NC) sublayer at the Radio Link Control/Multiple Access Control (RLC/MAC) layer boundary within the 3GPP Long Term Evolution (LTE) Radio Access Network (RAN) protocol stack. R-NC is introduced as a simple alternative to the MAC/Physical Layer (PHY) Hybrid Automatic...

    Provided By University of Economics, Prague

  • White Papers // Mar 2012

    Coded Spatial Modulation Applied to Optical Wireless Communications in Indoor Environments

    Spatial Modulation (SM) is a combined Multiple-Input-Multiple-Output (MIMO) and digital modulation technique which besides common signal modulation conveys additional information bits in the spatial domain. To this end, only one transmitter is active at any time instance. The actual index of each emitter represents a unique spatial constellation point and...

    Provided By University of Economics, Prague

  • White Papers // Mar 2012

    Reasoning About Multi-process Systems with the Box Calculus

    The box calculus is a formalism for reasoning about the properties of multi-process systems which enables account to be taken of pragmatic as well as computational concerns. It was developed for the programming language Hume which explicitly distinguishes between co-ordination, based on concurrent boxes linked by wires, and expressions, based...

    Provided By University of Economics, Prague

  • White Papers // Feb 2012

    Energy-Efficient Subcarrier-and-Bit Allocation in Multi-User OFDMA Systems

    Energy efficiency is becoming increasingly important for wireless communication systems in order to minimize carbon footprint of wireless networks and to increase the battery life of mobile terminals. The spectral-energy efficiency trade-off is of primary significance to determine how much energy per bit is required in a wireless communication system...

    Provided By University of Economics, Prague

  • White Papers // Jan 2012

    Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs

    Intelligently partitioning the last-level cache within a Chip Multi-Processor (CMP) can bring significant performance improvements. Resources are given to the applications that can benefit most from them, restricting each core to a number of logical cache ways. However, although overall performance is increased, existing schemes fail to consider energy saving...

    Provided By University of Economics, Prague

  • White Papers // Jan 2012

    A New Method of Encoding Block Codes With Polynomials

    The authors present an efficient new method of obtaining a generator matrix G from certain types of parity check matrices H with a defective cyclic block structure. This novel approach describes parity check and generator matrices in terms of polynomials. Moreover, by using this polynomial algebra they have found efficient...

    Provided By University of Economics, Prague

  • White Papers // Aug 2011

    Towards Certain Fixes with Editing Rules and Master Data

    A variety of integrity constraints have been studied for data cleaning. While these constraints can detect the presence of errors, they fall short of guiding users to correct the errors. Indeed, data repairing based on these constraints may not find certain fixes that are guaranteed correct, and worse still, may...

    Provided By University of Economics, Prague

  • White Papers // Aug 2011

    Phase-Based Application-Driven Hierarchical Power Management on the Single-Chip Cloud Computer

    To improve energy efficiency processors allow for Dynamic Voltage and Frequency Scaling (DVFS), which enables changing their performance and power consumption on-the-fly. Many-core architectures, such as the Single-chip Cloud Computer (SCC) experimental processor from Intel Labs, have DVFS infrastructures that scale by having many more independent voltage and frequency domains...

    Provided By University of Economics, Prague

  • White Papers // Aug 2011

    Spectral-Energy Efficiency Tradeoff in Cognitive Radio Networks With Peak Interference Power Constraints

    Cognitive Radio (CR) is considered as one of the prominent techniques to improve the spectrum utilization by opportunistically sharing the radio spectrum resources with licensed users. This paper concentrates on characterizing the spectral-energy efficiency tradeoff in low and high Signal-to-Noise Ratio (SNR) regimes for interference-tolerant CR networks under peak interference...

    Provided By University of Economics, Prague

  • White Papers // Jun 2011

    Providing Dependability and Resilience in the Cloud: Challenges and Opportunities

    Computing is a novel paradigm for providing data center resources as on demand services in a pay-as-you-go manner. It promises significant cost savings by making it possible to consolidate workloads and share infrastructure resources among multiple applications resulting in higher cost- and energy-efficiency. In this paper, the authors first discuss...

    Provided By University of Economics, Prague

  • White Papers // Feb 2011

    Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency

    The power dissipation of modern microprocessors is a primary design constraint across all processing domains, from embedded devices to high performance chips. Shrinking feature sizes and increasing numbers of transistors packed into a single die only exacerbates this issue. Schemes are urgently required to tackle power dissipation, yet still deliver...

    Provided By University of Economics, Prague

  • White Papers // Dec 2010

    A Static Task Partitioning Approach for Heterogeneous Systems Using OpenCL

    Heterogeneous multi-core platforms are increasingly prevalent due to their perceived superior performance over homogeneous systems. The best performance, however, can only be achieved if tasks are accurately mapped to the right processors. OpenCL programs can be partitioned to take advantage of all the available processors in a system. However, finding...

    Provided By University of Economics, Prague

  • White Papers // Sep 2010

    A Predictive Model for Dynamic Microarchitectural Adaptivity Control

    Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resources to the specific requirements of different programs or program phases. They have the potential to adapt the hardware cost-effectively at runtime to any application's needs. However, one of the key challenges...

    Provided By University of Economics, Prague

  • White Papers // Dec 2009

    Case Study on Linked Data and SPARQL Usage for Web Application Development

    Most current websites are programmed to be human-readable only. Even if the websites are dynamically generated, all semantics of presented data is lost as they are published as (X)HTML pages. Although, people browsing the site typically understand data such as titles, author names, dates properly, the computers treat such pages...

    Provided By University of Economics, Prague

  • White Papers // Aug 2013

    Geometric Methods of Information Storage and Retrieval in Sensor Networks

    Sensor networks collect data from their environment. Locations of the sensors are important attributes of that information and provide a context to understand, and use sensor data. In this paper, the authors will discuss geometric ideas to organize sensor data using their locations. They will consider distributed methods for managing...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    Tradeoffs in XML Database Compression

    Large XML data les, or XML databases, are now a common way to distribute scientific and bibliographic data and storing such data efficiently is an important concern. A number of approaches to XML compression have been proposed in the last five years. The most competitive approaches employ one or more...

    Provided By University of Economics, Prague

  • White Papers // Jul 2008

    Semantics-Based Process Support for Grid Applications

    The infrastructure of Grid is approaching maturity and can be used to enable the utilization and sharing of large scale, remote data storages through distributed computational capabilities and support collaborations and co-operations between different organizations. Grid can therefore be suitably used to support the creation and running of a Virtual...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    TSO-CC: Consistency Directed Cache Coherence for TSO

    Traditional directory coherence protocols are designed for the strictest consistency model, Sequential Consistency (SC). When they are used for Chip Multi-Processors (CMPs) that support relaxed memory consistency models, such protocols turn out to be unnecessarily strict. Usually this comes at the cost of scalability, which poses a problem with increasing...

    Provided By University of Economics, Prague

  • White Papers // Jun 2009

    Compiler Directed Issue Queue Energy Reduction

    Superscalar processors contain complex logic to hold instructions and information as they pass through the pipeline. The issue logic of a superscalar processor consumes a large amount of static and dynamic energy. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. This paper presents...

    Provided By University of Economics, Prague

  • White Papers // Dec 2012

    Position Paper: Weak Heterogeneity as a Way of Adapting Multicores to Real Workloads

    There is a growing consensus that heterogeneous multicores are the future of CPUs. These processors would be composed of cores that are specifically adapted or tuned to particular types of applications and use cases, thereby increasing performance. The move from homogeneous to heterogeneous multicores causes the design space to explode,...

    Provided By University of Economics, Prague

  • White Papers // Feb 2013

    CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

    Aggressive silicon process scaling over the last years has made transistors faster and less power consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors. In this...

    Provided By University of Economics, Prague

  • White Papers // Jan 2014

    The Design and Performance of a Conflict-Avoiding Cache

    High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. In this paper, the authors investigate the...

    Provided By University of Economics, Prague

  • White Papers // Sep 2013

    OpenCL Task Partitioning in the Presence of GPU Contention

    Heterogeneous multi- and many-core systems are increasingly prevalent in the desktop and mobile domains. On these systems it is common for programs to compete with co-running programs for resources. While multi-task scheduling for CPUs is a well-studied area, how to partitioning and map computing tasks onto the heterogeneous system in...

    Provided By University of Economics, Prague

  • White Papers // Dec 2010

    A Static Task Partitioning Approach for Heterogeneous Systems Using OpenCL

    Heterogeneous multi-core platforms are increasingly prevalent due to their perceived superior performance over homogeneous systems. The best performance, however, can only be achieved if tasks are accurately mapped to the right processors. OpenCL programs can be partitioned to take advantage of all the available processors in a system. However, finding...

    Provided By University of Economics, Prague

  • White Papers // Jan 2010

    Static Java Program Features for Intelligent Squash Prediction

    The thread-level speculation paradigm parallelizes sequential applications at run-time, via optimistic execution of potentially independent threads. This paper enables unmodified sequential applications to exploit thread-level parallelism on modern multicore architectures. However a high frequency of data dependence violations between speculative threads can severely degrade the performance of thread-level speculation. Thus...

    Provided By University of Economics, Prague

  • White Papers // Aug 2011

    Phase-Based Application-Driven Hierarchical Power Management on the Single-Chip Cloud Computer

    To improve energy efficiency processors allow for Dynamic Voltage and Frequency Scaling (DVFS), which enables changing their performance and power consumption on-the-fly. Many-core architectures, such as the Single-chip Cloud Computer (SCC) experimental processor from Intel Labs, have DVFS infrastructures that scale by having many more independent voltage and frequency domains...

    Provided By University of Economics, Prague

  • White Papers // Jul 2012

    Inferring Data Currency and Consistency for Conflict Resolution

    In this paper, the authors introduce a new approach for conflict resolution: given a set of tuples pertaining to the same entity, it is to identify a single tuple in which each attribute has the latest and consistent value in the set. This problem is important in data integration, data...

    Provided By University of Economics, Prague

  • White Papers // May 2006

    Do Not Crawl in the DUST: Different URLs With Similar Text Extended Abstract

    The authors consider the problem of dust: different URLs with similar text. Such duplicate URLs are prevalent in web sites, as web server software often uses aliases and redirections, translates URLs to some canonical form, and dynamically generates the same page from various different URL requests. They present a novel...

    Provided By University of Economics, Prague

  • White Papers // Jun 2008

    High-Performance Low-Power FFT Cores

    Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as Fast Fourier Transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer...

    Provided By University of Economics, Prague

  • White Papers // Aug 2008

    Maxwell - a 64 FPGA Supercomputer

    The authors describe the FPGA-based supercomputer Maxwell built by the FPGA high-performance computing alliance at the University of Edinburgh. Winner of the silver medal in the BT Flagship Award for Innovation at the 2007 British Computer Society Awards, Maxwell is a general-purpose 64 FPGA computer designed for high-performance parallel computing....

    Provided By University of Economics, Prague

  • White Papers // Aug 2008

    High Performance Monte-Carlo Based Option Pricing on FPGAs

    High performance computing is becoming increasingly important in the field of financial computing, as the complexity of financial models continues to increase. Many of these financial models do not have a practical close form solution in which case numerical methods are the only alternative. Monte-Carlo simulation is one of most...

    Provided By University of Economics, Prague

  • White Papers // Aug 2008

    Design and Implementation of an FPGA-based Core for Gapped BLAST Sequence Alignment with the Two-Hit Method

    In this paper, the authors present the design and implementation of the first FPGA-based core for Gapped BLAST sequence alignment with the two-hit method, ever reported in the literature. Gapped BLAST with two hit is a heuristic biological sequence alignment algorithm which is very widely used in the bioinformatics and...

    Provided By University of Economics, Prague

  • White Papers // Mar 2012

    Reasoning About Multi-process Systems with the Box Calculus

    The box calculus is a formalism for reasoning about the properties of multi-process systems which enables account to be taken of pragmatic as well as computational concerns. It was developed for the programming language Hume which explicitly distinguishes between co-ordination, based on concurrent boxes linked by wires, and expressions, based...

    Provided By University of Economics, Prague

  • White Papers // Mar 2013

    V-BOINC: The Virtualization of BOINC

    The Berkeley Open Infrastructure for Network Computing (BOINC) is an open source client-server middleware system created to allow projects with large computational requirements, usually set in the scientific domain, to utilize a technically unlimited number of volunteer machines distributed over large physical distances. However, various problems exist deploying applications over...

    Provided By University of Economics, Prague

  • White Papers // Aug 2012

    The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

    The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and...

    Provided By University of Economics, Prague

  • White Papers // Feb 2008

    Fast Source-Level Data Assignment to Dual Memory Banks

    Digital signal processors are domain specific microprocessors optimized for embedded digital signal processing applications. The demand for high performance, low power and low cost has led to the development of specialized architectures with many non-standard features exposed to the programmer. With the recent trend towards more complex signal processing algorithms...

    Provided By University of Economics, Prague

  • White Papers // Dec 2007

    Evaluating the Effects of Compiler Optimisations on AVF

    Transient faults are becoming more of a problem to processor designers as feature sizes shrink and the number of transistors on a chip increases. Significant research has focused on hardware techniques to evaluate and reduce the architectural vulnerability to soft errors. This paper, however, considers the problem from a different...

    Provided By University of Economics, Prague

  • White Papers // Feb 2011

    Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency

    The power dissipation of modern microprocessors is a primary design constraint across all processing domains, from embedded devices to high performance chips. Shrinking feature sizes and increasing numbers of transistors packed into a single die only exacerbates this issue. Schemes are urgently required to tackle power dissipation, yet still deliver...

    Provided By University of Economics, Prague

  • White Papers // Sep 2010

    A Predictive Model for Dynamic Microarchitectural Adaptivity Control

    Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resources to the specific requirements of different programs or program phases. They have the potential to adapt the hardware cost-effectively at runtime to any application's needs. However, one of the key challenges...

    Provided By University of Economics, Prague

  • White Papers // Jan 2008

    A Generic Tool Supporting Cache Design and Optimisation on Shared Memory Systems

    For multi-core architectures, improving the cache performance is crucial for the overall system performance. In contrast to the common approach to design caches with the best trade-off between performance and costs, this paper favors an application specific cache design. Therefore, an analysis tool capable of exhibiting the reason of cache...

    Provided By University of Economics, Prague

  • White Papers // Jan 2009

    Using Genetic Programming for Source-Level Data Assignment to Dual Memory Banks

    Due to their streaming nature, memory bandwidth is critical for most digital signal processing applications. To accommodate these bandwidth requirements Digital Signal Processors (DSP) are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches...

    Provided By University of Economics, Prague

  • White Papers // Jul 2009

    Machine Models for Query Processing

    The massive data sets that have to be processed in many application areas are often far too large to fit completely into a computer's internal memory. When evaluating queries on such large data sets, the resulting communication between fast internal memory and slower external memory turns out to be a...

    Provided By University of Economics, Prague

  • White Papers // Feb 2007

    Synthetic Trace-Driven Simulation of Cache Memory

    The widening gap between CPU and memory speed has made caches an integral feature of modern high-performance processors. The high degree of configurability of cache memory can require extensive design space exploration and is generally performed using execution-driven or trace-driven simulation. Execution-driven simulators can be highly accurate but require a...

    Provided By University of Economics, Prague

  • White Papers // Aug 2012

    UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

    Clustered VLIW processors are scalable wide-issue statically scheduled processors. Their design is based on physically partitioning the otherwise shared hardware resources, a design which leads to both high performance and low energy consumption. In traditional clustered VLIW processors, all clusters operate at the same frequency. Heterogeneous clustered VLIW processors however,...

    Provided By University of Economics, Prague

  • White Papers // Jul 2014

    Business Rule Learning with Interactive Selection of Association Rules

    Today, there is an increasing demand for Decision Support Systems (DSS). The penetration of DSS solutions to many domains is stifled by the fact that building a DSS requires a significant amount of time from users, who need to be not only domain experts, but also skilled knowledge engineers. This...

    Provided By University of Economics, Prague

  • White Papers // Jul 2013

    CAeSaR: Unified Cluster-Assignment Scheduling and Communication Reuse for Clustered VLIW Processors

    Clustered architectures have been proposed as a solution to the scalability problem of wide ILP processors. VLIW architectures, being wide-issue by design, benefit significantly from clustering. Such architectures, being both statically scheduled and clustered, require specialized code generation techniques, as they require explicit Inter-Cluster Copy instructions (ICCs) be scheduled in...

    Provided By University of Economics, Prague

  • White Papers // May 2009

    Resource Sharing in Custom Instruction Set Extensions

    Customized processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency is equally important. Resource sharing during synthesis of Instruction Set Extensions (ISEs) can reduce significantly the die area and energy...

    Provided By University of Economics, Prague

  • White Papers // Dec 2008

    An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection Based on GCC

    Extensible processors are Application-Specific Instruction set Processors (ASIPs) that allow for customization through user-defined Instruction Set Extensions (ISE) implemented in an extended micro architecture. Traditional design flows for ISE typically involve a large number of different tools for processing of the target application written in C, ISE identification, generation, optimization...

    Provided By University of Economics, Prague

  • White Papers // Feb 2010

    Profitability-Based Power Allocation for Speculative Multithreaded Systems

    With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional out-of-order processors, multi-core systems are becoming the design choice for industry. Performance extraction is thus largely alleviated from the hardware and placed on the programmer/compiler camp, which now have to expose Thread Level Parallelism (TLP)...

    Provided By University of Economics, Prague

  • White Papers // Aug 2009

    Rapid Early-Stage Microarchitecture Design Using Predictive Models

    The early-stage design of a new microprocessor involves the evaluation of a wide range of benchmarks across a large number of architectural configurations. Several methods are used to cut down on the required simulation time. Typically, however, existing approaches fail to capture true program behavior accurately and require a non-negligible...

    Provided By University of Economics, Prague

  • White Papers // Jan 2012

    Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs

    Intelligently partitioning the last-level cache within a Chip Multi-Processor (CMP) can bring significant performance improvements. Resources are given to the applications that can benefit most from them, restricting each core to a number of logical cache ways. However, although overall performance is increased, existing schemes fail to consider energy saving...

    Provided By University of Economics, Prague

  • White Papers // Jun 2007

    Combining Source- Level Transformations and Instruction Set Extension

    High performance and short time-to-market are two of the major factors in embedded systems design. In recent years, processor IP vendors have addressed these by developing configurable and extensible processors such as the ARC 600 and 700, Tensilica Xtensa, ARM OptimoDE, and the MIPS Pro. These cores provide system designers...

    Provided By University of Economics, Prague

  • White Papers // Sep 2007

    Microarchitectural Design Space Exploration Using An Architecture-Centric Approach

    The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a single configuration can take excessive time due to the need to run a set of benchmarks with realistic workloads. This paper...

    Provided By University of Economics, Prague