University of Neuchatel

Displaying 1-8 of 8 results

  • White Papers // May 2012

    Path-Vector Contract Routing

    Many recently proposed clean slate Internet architectures essentially depend on more flexible and extended representation of Internet topology on which next generation routing protocols may operate. Representation of neighboring relationships between Internet Service Providers (ISPs) in finer granularity is promising to overcome many shortcomings of the current Internet architecture. Similarly,...

    Provided By University of Neuchatel

  • White Papers // May 2012

    ISPs as Nodes or Sets of Links?

    The authors consider the contract-switching paradigm for studying the inter-domain traffic engineering problem. In the contract-switching paradigm, each ISP in the Internet is abstracted as a set of edge-to-edge contract links. They formulate the optimal routing problem for the contract-switching paradigm by considering three objectives, namely: maximizing throughput, minimizing delay,...

    Provided By University of Neuchatel

  • White Papers // May 2011

    On a Scalable, Non-Blocking Optical Router for Photonic Networks-on-Chip Designs

    Photonic Networks-on-Chip (NoC) is considered as a promising candidate to interconnect a large number of processing cores. The heart of a photonic NoC is the on-chip photonic interconnection network which is composed of silicon waveguides and optical routers. In this paper, the authors propose a scalable and non-blocking passive optical...

    Provided By University of Neuchatel

  • White Papers // Oct 2010

    Building a Multi-FPGA-Based Emulation Framework to Support Networks-on-Chip Design and Verification

    In this paper, the authors present a highly scalable, flexible hardware-based Network-on-Chip (NoC) emulation framework, through which NoCs built upon various types of network topologies, routing algorithms, switching protocols and flow control schemes can be explored, compared, and validated with injected or self-generated traffic from both real-life and synthetic applications....

    Provided By University of Neuchatel

  • White Papers // Jan 2008

    Deadlock-Free Multi-Path Routing for Torus-Based NoCs

    In this paper, the authors present the Multi-Path Routing (MPR) scheme was proposed to maximize the data throughput for torus-based NoCs by utilizing multiple paths for concurrent data transmission. In this paper, a deadlock-free virtual channel model is proposed for the MPR scheme. In this virtual channel model, every physical...

    Provided By University of Neuchatel

  • White Papers // Oct 2007

    A Multi-Path Routing Scheme for Torus-Based NoCs

    In Networks-on-Chip (NoC) designs, crosstalk noise has become a serious issue which may cause the communication channel unreliable. The crosstalk problem can be mitigated by wide spacing of serial lines. However, the wider spacing of serial lines will reduce the number of the lines, thus reduce the data throughput. In...

    Provided By University of Neuchatel

  • White Papers // Jul 2007

    Knowledge States for the Caching Problem in Shared Memory Multiprocessor Systems

    Multiprocessor systems with a global shared memory provide logically uniform data access. To hide latencies when accessing global memory each processor makes use of a private cache. Several copies of a data item may exist concurrently in the system. To guarantee consistency when updating an item a processor must invalidate...

    Provided By University of Neuchatel

  • White Papers // Jan 2007

    Multi-path Routing for Mesh/Torus-Based NoCs

    In Network-on-Chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the increasing switching speed. The crosstalk between adjacent lines causes data dependent signal delay and noise, thus finally makes the communication channel unreliable. The crosstalk problem can...

    Provided By University of Neuchatel

  • White Papers // May 2012

    Path-Vector Contract Routing

    Many recently proposed clean slate Internet architectures essentially depend on more flexible and extended representation of Internet topology on which next generation routing protocols may operate. Representation of neighboring relationships between Internet Service Providers (ISPs) in finer granularity is promising to overcome many shortcomings of the current Internet architecture. Similarly,...

    Provided By University of Neuchatel

  • White Papers // May 2012

    ISPs as Nodes or Sets of Links?

    The authors consider the contract-switching paradigm for studying the inter-domain traffic engineering problem. In the contract-switching paradigm, each ISP in the Internet is abstracted as a set of edge-to-edge contract links. They formulate the optimal routing problem for the contract-switching paradigm by considering three objectives, namely: maximizing throughput, minimizing delay,...

    Provided By University of Neuchatel

  • White Papers // Oct 2010

    Building a Multi-FPGA-Based Emulation Framework to Support Networks-on-Chip Design and Verification

    In this paper, the authors present a highly scalable, flexible hardware-based Network-on-Chip (NoC) emulation framework, through which NoCs built upon various types of network topologies, routing algorithms, switching protocols and flow control schemes can be explored, compared, and validated with injected or self-generated traffic from both real-life and synthetic applications....

    Provided By University of Neuchatel

  • White Papers // Jan 2008

    Deadlock-Free Multi-Path Routing for Torus-Based NoCs

    In this paper, the authors present the Multi-Path Routing (MPR) scheme was proposed to maximize the data throughput for torus-based NoCs by utilizing multiple paths for concurrent data transmission. In this paper, a deadlock-free virtual channel model is proposed for the MPR scheme. In this virtual channel model, every physical...

    Provided By University of Neuchatel

  • White Papers // Jan 2007

    Multi-path Routing for Mesh/Torus-Based NoCs

    In Network-on-Chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the increasing switching speed. The crosstalk between adjacent lines causes data dependent signal delay and noise, thus finally makes the communication channel unreliable. The crosstalk problem can...

    Provided By University of Neuchatel

  • White Papers // Jul 2007

    Knowledge States for the Caching Problem in Shared Memory Multiprocessor Systems

    Multiprocessor systems with a global shared memory provide logically uniform data access. To hide latencies when accessing global memory each processor makes use of a private cache. Several copies of a data item may exist concurrently in the system. To guarantee consistency when updating an item a processor must invalidate...

    Provided By University of Neuchatel

  • White Papers // Oct 2007

    A Multi-Path Routing Scheme for Torus-Based NoCs

    In Networks-on-Chip (NoC) designs, crosstalk noise has become a serious issue which may cause the communication channel unreliable. The crosstalk problem can be mitigated by wide spacing of serial lines. However, the wider spacing of serial lines will reduce the number of the lines, thus reduce the data throughput. In...

    Provided By University of Neuchatel

  • White Papers // May 2011

    On a Scalable, Non-Blocking Optical Router for Photonic Networks-on-Chip Designs

    Photonic Networks-on-Chip (NoC) is considered as a promising candidate to interconnect a large number of processing cores. The heart of a photonic NoC is the on-chip photonic interconnection network which is composed of silicon waveguides and optical routers. In this paper, the authors propose a scalable and non-blocking passive optical...

    Provided By University of Neuchatel