University of Paris 13

Displaying 1-26 of 26 results

  • White Papers // Jan 2014

    Stereovision-Based 3D Obstacle Detection for Automotive Safety Driving Assistance

    In this paper, the authors describe the implementation of a real-time architecture dedicated to obstacle detection in the automotive domain, and more particularly to pre-crash situations. The method, based on stereovision, is of high complexity and cannot run in real-time on standard processors. Therefore, the application is accelerated with the...

    Provided By University of Paris 13

  • White Papers // Jan 2014

    High Level Power and Energy Exploration Using ArchC

    With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. The authors propose a methodology using ArchC named power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level...

    Provided By University of Paris 13

  • White Papers // Nov 2013

    Efficient and Truthful Bandwidth Allocation in Wireless Mesh Community Networks

    Now-a-days, the maintenance costs of wireless devices represent one of the main limitations to the deployment of Wireless Mesh Networks (WMN) as a means to provide Internet access in urban and rural areas. A promising solution to this issue is to let the Wireless Mesh Network (WMN) operator lease its...

    Provided By University of Paris 13

  • White Papers // Jul 2012

    Joint Rate Adaptation and Medium Access in Wireless LANs: A Non-Cooperative Game Theoretic Perspective

    Wireless Local Area Networks (WLANs) based on IEEE 802.11 standards are becoming ubiquitous today and typically support multiple data rates. In such multi-rate WLANs, distributed medium access and rate adaptation are two key elements to achieve efficient radio resource utilization, especially in non-cooperative environments. In this paper, the authors present...

    Provided By University of Paris 13

  • White Papers // May 2012

    Relation Between HCI-Induced Performance Degradation and Applications in a RISC Processor

    Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter Hot Carrier Injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the...

    Provided By University of Paris 13

  • White Papers // Nov 2011

    A Note on Semi-Bent Functions With Multiple Trace Terms and Hyperelliptic Curves

    Semi-bent functions with even number of variables are a class of important Boolean functions whose Hadamard transform takes three values. The authors subsequently give a connection between the property of semi-bentness and the number of rational points on some associated hyperelliptic curves. They use the hyperelliptic curve formalism to reduce...

    Provided By University of Paris 13

  • White Papers // Oct 2011

    A Small Footprint Interleaved Multithreaded Processor for Embedded Systems

    In this paper, the authors present a small footprint, scalar, in-order, 5-stage pipeline, interleaved multithreaded processor with 2 hardware thread contexts for embedded systems and SoC integration. With the increase in the design complexity of MPSoC architectures and the need for more transistor/energy efficient processor architectures, designers are exploiting the...

    Provided By University of Paris 13

  • White Papers // Sep 2011

    AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip

    The future high-end embedded systems applications are characterized by their computation-intensive workloads, their high-level of parallelism, their large data-set requirements, and their dynamism. Those applications require highly-efficient manycore architectures. In response to this problem, the authors designed an asymmetric homogeneous with dynamic allocator manycore architecture, called AHDAM chip. AHDAM chip...

    Provided By University of Paris 13

  • White Papers // Jul 2011

    A SystemC TLM Framework for Distributed Simulation of Complex Systems with Unpredictable Communication

    Increasingly complex systems need parallelized simulation engines. In the context of SystemC simulation, existing proposals require predicting communication in the simulated system. However, this is often unpredictable. In order to deal with unpredictable systems, this paper presents a parallelization approach using asynchronous communication without modification of the SystemC simulation engine....

    Provided By University of Paris 13

  • White Papers // May 2011

    Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems

    Future embedded systems will have to support multiple and concurrent dynamic compute-intensive applications. These variable workloads can be handled by an efficient asymmetric MPSoC architecture, which integrates multithreaded processors as key processing elements. In this paper, the authors consider an asymmetric MPSoC architecture with a centralized controller and multiple multithreaded...

    Provided By University of Paris 13

  • White Papers // Apr 2011

    System Level Analysis and Accurate Prediction of Electromigration

    A single chip or a system can have more than billions of transistors, and billions of via connected through miles of interconnections. This paper aims at analyzing dynamic variations and then hard failures due to electro migration at functional level and to estimate the accuracy of the reliability aware ArchC...

    Provided By University of Paris 13

  • White Papers // Feb 2011

    Impact of the Application Activity on Intermittent Faults in Embedded Systems

    Future embedded systems are going to be more sensitive to hardware faults. In particular, intermittent faults are going to appear faster in future technologies. Understanding the occurrence of faults and their impact on systems and applications can help to improve the fault-tolerance of systems. However, there is no study on...

    Provided By University of Paris 13

  • White Papers // Dec 2010

    A TLM-Based Multithreaded Instruction Set Simulator for MPSoC Simulation Environment

    With the increase in the design complexity of MPSoC architectures, flexible and accurate processor simulators become a necessity for exploring the vast design space solutions. In this paper, the authors present a flexible multithreaded ISS model based on a modular cycle-accurate modeling technique. The model is scalable for n hardware...

    Provided By University of Paris 13

  • White Papers // Nov 2010

    Quantitative Model for Evaluate Routing Protocols in a Vehicular Ad Hoc Networks on Highway

    The authors' main goal is to provide the best management protocols for Vehicular Ad Hoc NETwork (VANET), more precisely, to determine the best routing protocol. In this paper, they focus on VANET built on highway where cars run in the same direction. They introduce a quantitative model in order to...

    Provided By University of Paris 13

  • White Papers // Oct 2010

    RAAPS: Reliability Aware ArchC Based Processor Simulator

    In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing...

    Provided By University of Paris 13

  • White Papers // Jul 2010

    SESAM Extension for Fast MPSoC Architectural Exploration and Dynamic Streaming Applications

    Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these computation needs, only multithreaded approaches are possible. Thus, the support of a streaming execution model is very important for dataflow applications. However, with dynamic applications, each execution stage...

    Provided By University of Paris 13

  • White Papers // Jun 2010

    A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC

    As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs. The issue for multiprocessor architectures is to optimize the processing re-sources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue, the authors...

    Provided By University of Paris 13

  • White Papers // May 2010

    SESAM: An MPSoC Simulation Environment for Dynamic Application Processing

    Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this...

    Provided By University of Paris 13

  • White Papers // Apr 2010

    Analysis of On-Line Self-Testing Policies for Real-Time Embedded Multiprocessors in Dsm Technologies

    Advances in DSM technologies have a negative impact on yield and reliability of digital circuits. On-line self-testing is an interesting solution for detecting permanent and intermittent faults in non safety critical and real-time embedded multiprocessors. In this paper, the authors describe and evaluate three scheduling and allocation policies for on-line...

    Provided By University of Paris 13

  • White Papers // Apr 2010

    Towards a Parameterizable Cycle-Accurate ISS in ArchC

    With the increase in the design complexity of MPSoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, the authors present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and...

    Provided By University of Paris 13

  • White Papers // Mar 2010

    Concurrent Processes as Wireless Proof Nets

    The authors present a proofs-as-programs correspondence between linear logic and process calculi that permits non-deterministic behaviors. Processes are translated into wireless proof nets, i.e. proof nets of multiplicative linear logic without cut wires. Typing a term using them consists in typing some of its possible determinisations in standard sequent calculus....

    Provided By University of Paris 13

  • White Papers // Mar 2010

    Hierarchical Network-on-Chip for Embedded Many-Core Architectures

    The need for computing power drastically increases and one good solution is to use many-core architectures. Besides, complex embedded applications become data-dependent and their execution time depends on their input data. For this reason, on-line task and data allocation is needed to optimize the architecture efficiency. Moreover, communications are a...

    Provided By University of Paris 13

  • White Papers // Dec 2009

    On-Line Pseudo-Periodic Testing for Embedded Multiprocessor

    Advances in integration technologies have a negative impact on reliability and detecting intermittent faults became a large challenge for complex systems like multicore processors. On-line periodic testing is a good candidate for the detection of intermittent errors but induces lots of preemptions to execute the tests and increase application time....

    Provided By University of Paris 13

  • White Papers // Nov 2009

    Low-Complex Task Scheduling Algorithms for Hierarchical Embedded Many-Core Architectures and Dynamic Applications

    Embedded systems require more and more computational power. Moreover, embedded applications are becoming data-dependent and their execution time depends on their input data. Only a dynamic global scheduling can balance the workload on the computation resources and reach good performances. Thus, a solution to address this problem is to use...

    Provided By University of Paris 13

  • White Papers // May 2009

    Approximate-Timed Transactional Level Modeling for MPSoC Exploration: a Network-on-Chip Case Study

    The need for computing power drastically increases and one solution is to use MPSoC. These MPSoCs become complex with the increase of the number of cores. Thus, designers use simulators to explore the whole platform parameters in order to define the best architecture. These simulators must be fast and accurate...

    Provided By University of Paris 13

  • White Papers // Sep 2007

    Effects of Various Applications on Relative LifeTime of Processor Cores

    The lifetime of integrated chip is reducing rapidly with technology. To check if design is feasible, and to study and analyze the lifetime of processor, via studying failure mechanisms on higher level of abstraction layer, the authors present an interesting idea to evaluate reliability using RTME (Real Time MTTF Evaluation)...

    Provided By University of Paris 13

  • White Papers // Mar 2010

    Concurrent Processes as Wireless Proof Nets

    The authors present a proofs-as-programs correspondence between linear logic and process calculi that permits non-deterministic behaviors. Processes are translated into wireless proof nets, i.e. proof nets of multiplicative linear logic without cut wires. Typing a term using them consists in typing some of its possible determinisations in standard sequent calculus....

    Provided By University of Paris 13

  • White Papers // Nov 2011

    A Note on Semi-Bent Functions With Multiple Trace Terms and Hyperelliptic Curves

    Semi-bent functions with even number of variables are a class of important Boolean functions whose Hadamard transform takes three values. The authors subsequently give a connection between the property of semi-bentness and the number of rational points on some associated hyperelliptic curves. They use the hyperelliptic curve formalism to reduce...

    Provided By University of Paris 13

  • White Papers // Nov 2010

    Quantitative Model for Evaluate Routing Protocols in a Vehicular Ad Hoc Networks on Highway

    The authors' main goal is to provide the best management protocols for Vehicular Ad Hoc NETwork (VANET), more precisely, to determine the best routing protocol. In this paper, they focus on VANET built on highway where cars run in the same direction. They introduce a quantitative model in order to...

    Provided By University of Paris 13

  • White Papers // Jul 2012

    Joint Rate Adaptation and Medium Access in Wireless LANs: A Non-Cooperative Game Theoretic Perspective

    Wireless Local Area Networks (WLANs) based on IEEE 802.11 standards are becoming ubiquitous today and typically support multiple data rates. In such multi-rate WLANs, distributed medium access and rate adaptation are two key elements to achieve efficient radio resource utilization, especially in non-cooperative environments. In this paper, the authors present...

    Provided By University of Paris 13

  • White Papers // Nov 2013

    Efficient and Truthful Bandwidth Allocation in Wireless Mesh Community Networks

    Now-a-days, the maintenance costs of wireless devices represent one of the main limitations to the deployment of Wireless Mesh Networks (WMN) as a means to provide Internet access in urban and rural areas. A promising solution to this issue is to let the Wireless Mesh Network (WMN) operator lease its...

    Provided By University of Paris 13

  • White Papers // Jul 2011

    A SystemC TLM Framework for Distributed Simulation of Complex Systems with Unpredictable Communication

    Increasingly complex systems need parallelized simulation engines. In the context of SystemC simulation, existing proposals require predicting communication in the simulated system. However, this is often unpredictable. In order to deal with unpredictable systems, this paper presents a parallelization approach using asynchronous communication without modification of the SystemC simulation engine....

    Provided By University of Paris 13

  • White Papers // May 2009

    Approximate-Timed Transactional Level Modeling for MPSoC Exploration: a Network-on-Chip Case Study

    The need for computing power drastically increases and one solution is to use MPSoC. These MPSoCs become complex with the increase of the number of cores. Thus, designers use simulators to explore the whole platform parameters in order to define the best architecture. These simulators must be fast and accurate...

    Provided By University of Paris 13

  • White Papers // Apr 2010

    Towards a Parameterizable Cycle-Accurate ISS in ArchC

    With the increase in the design complexity of MPSoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, the authors present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and...

    Provided By University of Paris 13

  • White Papers // Oct 2011

    A Small Footprint Interleaved Multithreaded Processor for Embedded Systems

    In this paper, the authors present a small footprint, scalar, in-order, 5-stage pipeline, interleaved multithreaded processor with 2 hardware thread contexts for embedded systems and SoC integration. With the increase in the design complexity of MPSoC architectures and the need for more transistor/energy efficient processor architectures, designers are exploiting the...

    Provided By University of Paris 13

  • White Papers // May 2010

    SESAM: An MPSoC Simulation Environment for Dynamic Application Processing

    Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this...

    Provided By University of Paris 13

  • White Papers // May 2011

    Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems

    Future embedded systems will have to support multiple and concurrent dynamic compute-intensive applications. These variable workloads can be handled by an efficient asymmetric MPSoC architecture, which integrates multithreaded processors as key processing elements. In this paper, the authors consider an asymmetric MPSoC architecture with a centralized controller and multiple multithreaded...

    Provided By University of Paris 13

  • White Papers // Dec 2009

    On-Line Pseudo-Periodic Testing for Embedded Multiprocessor

    Advances in integration technologies have a negative impact on reliability and detecting intermittent faults became a large challenge for complex systems like multicore processors. On-line periodic testing is a good candidate for the detection of intermittent errors but induces lots of preemptions to execute the tests and increase application time....

    Provided By University of Paris 13

  • White Papers // Apr 2010

    Analysis of On-Line Self-Testing Policies for Real-Time Embedded Multiprocessors in Dsm Technologies

    Advances in DSM technologies have a negative impact on yield and reliability of digital circuits. On-line self-testing is an interesting solution for detecting permanent and intermittent faults in non safety critical and real-time embedded multiprocessors. In this paper, the authors describe and evaluate three scheduling and allocation policies for on-line...

    Provided By University of Paris 13

  • White Papers // Sep 2007

    Effects of Various Applications on Relative LifeTime of Processor Cores

    The lifetime of integrated chip is reducing rapidly with technology. To check if design is feasible, and to study and analyze the lifetime of processor, via studying failure mechanisms on higher level of abstraction layer, the authors present an interesting idea to evaluate reliability using RTME (Real Time MTTF Evaluation)...

    Provided By University of Paris 13

  • White Papers // Oct 2010

    RAAPS: Reliability Aware ArchC Based Processor Simulator

    In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing...

    Provided By University of Paris 13

  • White Papers // May 2012

    Relation Between HCI-Induced Performance Degradation and Applications in a RISC Processor

    Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter Hot Carrier Injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the...

    Provided By University of Paris 13

  • White Papers // Sep 2011

    AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip

    The future high-end embedded systems applications are characterized by their computation-intensive workloads, their high-level of parallelism, their large data-set requirements, and their dynamism. Those applications require highly-efficient manycore architectures. In response to this problem, the authors designed an asymmetric homogeneous with dynamic allocator manycore architecture, called AHDAM chip. AHDAM chip...

    Provided By University of Paris 13

  • White Papers // Jan 2014

    Stereovision-Based 3D Obstacle Detection for Automotive Safety Driving Assistance

    In this paper, the authors describe the implementation of a real-time architecture dedicated to obstacle detection in the automotive domain, and more particularly to pre-crash situations. The method, based on stereovision, is of high complexity and cannot run in real-time on standard processors. Therefore, the application is accelerated with the...

    Provided By University of Paris 13

  • White Papers // Jun 2010

    A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC

    As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs. The issue for multiprocessor architectures is to optimize the processing re-sources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue, the authors...

    Provided By University of Paris 13

  • White Papers // Mar 2010

    Hierarchical Network-on-Chip for Embedded Many-Core Architectures

    The need for computing power drastically increases and one good solution is to use many-core architectures. Besides, complex embedded applications become data-dependent and their execution time depends on their input data. For this reason, on-line task and data allocation is needed to optimize the architecture efficiency. Moreover, communications are a...

    Provided By University of Paris 13

  • White Papers // Dec 2010

    A TLM-Based Multithreaded Instruction Set Simulator for MPSoC Simulation Environment

    With the increase in the design complexity of MPSoC architectures, flexible and accurate processor simulators become a necessity for exploring the vast design space solutions. In this paper, the authors present a flexible multithreaded ISS model based on a modular cycle-accurate modeling technique. The model is scalable for n hardware...

    Provided By University of Paris 13

  • White Papers // Nov 2009

    Low-Complex Task Scheduling Algorithms for Hierarchical Embedded Many-Core Architectures and Dynamic Applications

    Embedded systems require more and more computational power. Moreover, embedded applications are becoming data-dependent and their execution time depends on their input data. Only a dynamic global scheduling can balance the workload on the computation resources and reach good performances. Thus, a solution to address this problem is to use...

    Provided By University of Paris 13

  • White Papers // Jan 2014

    High Level Power and Energy Exploration Using ArchC

    With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. The authors propose a methodology using ArchC named power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level...

    Provided By University of Paris 13

  • White Papers // Jul 2010

    SESAM Extension for Fast MPSoC Architectural Exploration and Dynamic Streaming Applications

    Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these computation needs, only multithreaded approaches are possible. Thus, the support of a streaming execution model is very important for dataflow applications. However, with dynamic applications, each execution stage...

    Provided By University of Paris 13

  • White Papers // Apr 2011

    System Level Analysis and Accurate Prediction of Electromigration

    A single chip or a system can have more than billions of transistors, and billions of via connected through miles of interconnections. This paper aims at analyzing dynamic variations and then hard failures due to electro migration at functional level and to estimate the accuracy of the reliability aware ArchC...

    Provided By University of Paris 13

  • White Papers // Feb 2011

    Impact of the Application Activity on Intermittent Faults in Embedded Systems

    Future embedded systems are going to be more sensitive to hardware faults. In particular, intermittent faults are going to appear faster in future technologies. Understanding the occurrence of faults and their impact on systems and applications can help to improve the fault-tolerance of systems. However, there is no study on...

    Provided By University of Paris 13