University of Siegen

Displaying 1-13 of 13 results

  • White Papers // Jun 2012

    Simulation Infrastructure for the Next Kilo-X86-64 Chips

    The enhancement in silicon technology facilitates the integration of a higher number of cores on a single chip. Considering the current CMOS integration technology tendency; in the next future, systems are expected to scale up the number of cores, resulting in architectures composed by thousands of cores (i.e., namely kilo-core...

    Provided By University of Siegen

  • White Papers // May 2012

    Distributed Duty Cycling Optimization for Asynchronous Wireless Sensor Networks

    One of the major sources of energy waste in a Wireless Sensor Network (WSN) is idle listening, i.e., the cost of actively listening for potential packets. This paper focuses on reducing the idle-listening time via a dynamic duty cycling technique which aims at optimizing the sleep interval between consecutive wakeups....

    Provided By University of Siegen

  • White Papers // Feb 2012

    Simulating the Future Kilo-X86-64 Core Processors and Their Infrastructure

    The continuous improvements offered by the silicon technology enables the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores in the next future. To cope with the increasing demand for high performance systems,...

    Provided By University of Siegen

  • White Papers // Feb 2012

    Language Composition Untangled

    In language-oriented programming and modeling, software developers are largely concerned with the definition of domain-specific languages (DSLs) and their composition. While various implementation techniques and frameworks exist for defining DSLs, language composition has not obtained enough attention and is not well-enough understood. In particular, there is a lack of precise...

    Provided By University of Siegen

  • White Papers // Jun 2011

    A Case Study on the Design Trade-Off of a Thread Level Data Flow Based Many-Core Architecture

    With the potential of overcoming the memory and power wall, the many-core/multi-thread has become a trend in processor design area. However, this architecture is far from ripeness because it also companies with many challenges such as scalability and larger architecture design space compared with mono-core architectures. In many-core design space,...

    Provided By University of Siegen

  • White Papers // Jul 2009

    Iterative Method for Improvement of Coding and Decryption

    Cryptographic check values (digital signatures, MACs and H-MACs) are useful only if they are free of errors. For that reason all of errors in cryptographic check values should be corrected after the transmission over a noisy channel before their verification is performed. Soft Input Decryption is a method of combining...

    Provided By University of Siegen

  • White Papers // Jun 2009

    Method to Improve Channel Coding Using Cryptography

    A new approach for the improvement of coding gain in channel coding using Advanced Encryption Standard (AES) and Maximum A Posteriori (MAP) algorithm is proposed. This new approach uses the avalanche effect of block cipher algorithm AES and soft output values of MAP decoding algorithm. The performance of proposed approach...

    Provided By University of Siegen

  • White Papers // Jun 2009

    Parallel Joint Channel Coding and Cryptography

    Method of Parallel Joint Channel Coding and Cryptography has been analyzed and simulated in this paper. The method is an extension of Soft Input Decryption with feedback, which is used for improvement of channel decoding of secured messages. Parallel Joint Channel Coding and Cryptography results in improved coding gain of...

    Provided By University of Siegen

  • White Papers // Jun 2009

    A Neural Network Classifier of Volume Datasets

    Many state-of-the art visualization techniques must be tailored to the specific type of dataset, its modality (CT, MRI, etc.), the recorded object or anatomical region (head, spine, abdomen, etc.) and other parameters related to the data acquisition process. While parts of the information (imaging modality and acquisition sequence) may be...

    Provided By University of Siegen

  • White Papers // Dec 2008

    Introducing Hardware TLP Support in the Cell Processor

    The authors' study is the support for fine/medium grained Thread Level Parallelism (TLP) by using a hardware scheduling unit and relying on existing simple cores. Simple cores are grouped into clusters in order to provide a scalable solution. As a proof of concept, they use an implementation based on the...

    Provided By University of Siegen

  • White Papers // Jan 2007

    Core Design and Scalability of Tiled SDF Architecture

    Embedded systems are using more extensively multi-core chips to reach high performance goals. While current systems contain only a few cores, present trends and commercial/research roadmaps foresee that in a near future many cores will be integrated on the same chip to achieve the best tradeoff between power consumption and...

    Provided By University of Siegen

  • White Papers // Jan 2007

    Scheduling and NoC Traffic Reduction in T-SDF Architecture

    As transistor size shrinks and chip complexity increases it is possible to place more transistor onto a single chip, and thus it is possible to integrate more than one processor on a single chip. Clock frequency is also increased, and because of wire delay it is not possible to reach...

    Provided By University of Siegen

  • White Papers // Jun 2006

    Elliptic Curve Cryptography Support for ARM Based Embedded Systems

    Elliptic Curve Cryptography (ECC) is emerging as an attractive approach to public-key cryptography for constrained environments, because of the small key sizes and computational efficiency, while preserving the same security level as the standard methods. The performance of public-key cryptography methods is critical in embedded environments such as applications for...

    Provided By University of Siegen

  • White Papers // Jul 2009

    Iterative Method for Improvement of Coding and Decryption

    Cryptographic check values (digital signatures, MACs and H-MACs) are useful only if they are free of errors. For that reason all of errors in cryptographic check values should be corrected after the transmission over a noisy channel before their verification is performed. Soft Input Decryption is a method of combining...

    Provided By University of Siegen

  • White Papers // Jun 2009

    A Neural Network Classifier of Volume Datasets

    Many state-of-the art visualization techniques must be tailored to the specific type of dataset, its modality (CT, MRI, etc.), the recorded object or anatomical region (head, spine, abdomen, etc.) and other parameters related to the data acquisition process. While parts of the information (imaging modality and acquisition sequence) may be...

    Provided By University of Siegen

  • White Papers // Jun 2009

    Method to Improve Channel Coding Using Cryptography

    A new approach for the improvement of coding gain in channel coding using Advanced Encryption Standard (AES) and Maximum A Posteriori (MAP) algorithm is proposed. This new approach uses the avalanche effect of block cipher algorithm AES and soft output values of MAP decoding algorithm. The performance of proposed approach...

    Provided By University of Siegen

  • White Papers // Jun 2009

    Parallel Joint Channel Coding and Cryptography

    Method of Parallel Joint Channel Coding and Cryptography has been analyzed and simulated in this paper. The method is an extension of Soft Input Decryption with feedback, which is used for improvement of channel decoding of secured messages. Parallel Joint Channel Coding and Cryptography results in improved coding gain of...

    Provided By University of Siegen

  • White Papers // Feb 2012

    Language Composition Untangled

    In language-oriented programming and modeling, software developers are largely concerned with the definition of domain-specific languages (DSLs) and their composition. While various implementation techniques and frameworks exist for defining DSLs, language composition has not obtained enough attention and is not well-enough understood. In particular, there is a lack of precise...

    Provided By University of Siegen

  • White Papers // May 2012

    Distributed Duty Cycling Optimization for Asynchronous Wireless Sensor Networks

    One of the major sources of energy waste in a Wireless Sensor Network (WSN) is idle listening, i.e., the cost of actively listening for potential packets. This paper focuses on reducing the idle-listening time via a dynamic duty cycling technique which aims at optimizing the sleep interval between consecutive wakeups....

    Provided By University of Siegen

  • White Papers // Dec 2008

    Introducing Hardware TLP Support in the Cell Processor

    The authors' study is the support for fine/medium grained Thread Level Parallelism (TLP) by using a hardware scheduling unit and relying on existing simple cores. Simple cores are grouped into clusters in order to provide a scalable solution. As a proof of concept, they use an implementation based on the...

    Provided By University of Siegen

  • White Papers // Jun 2011

    A Case Study on the Design Trade-Off of a Thread Level Data Flow Based Many-Core Architecture

    With the potential of overcoming the memory and power wall, the many-core/multi-thread has become a trend in processor design area. However, this architecture is far from ripeness because it also companies with many challenges such as scalability and larger architecture design space compared with mono-core architectures. In many-core design space,...

    Provided By University of Siegen

  • White Papers // Feb 2012

    Simulating the Future Kilo-X86-64 Core Processors and Their Infrastructure

    The continuous improvements offered by the silicon technology enables the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores in the next future. To cope with the increasing demand for high performance systems,...

    Provided By University of Siegen

  • White Papers // Jan 2007

    Core Design and Scalability of Tiled SDF Architecture

    Embedded systems are using more extensively multi-core chips to reach high performance goals. While current systems contain only a few cores, present trends and commercial/research roadmaps foresee that in a near future many cores will be integrated on the same chip to achieve the best tradeoff between power consumption and...

    Provided By University of Siegen

  • White Papers // Jan 2007

    Scheduling and NoC Traffic Reduction in T-SDF Architecture

    As transistor size shrinks and chip complexity increases it is possible to place more transistor onto a single chip, and thus it is possible to integrate more than one processor on a single chip. Clock frequency is also increased, and because of wire delay it is not possible to reach...

    Provided By University of Siegen

  • White Papers // Jun 2012

    Simulation Infrastructure for the Next Kilo-X86-64 Chips

    The enhancement in silicon technology facilitates the integration of a higher number of cores on a single chip. Considering the current CMOS integration technology tendency; in the next future, systems are expected to scale up the number of cores, resulting in architectures composed by thousands of cores (i.e., namely kilo-core...

    Provided By University of Siegen

  • White Papers // Jun 2006

    Elliptic Curve Cryptography Support for ARM Based Embedded Systems

    Elliptic Curve Cryptography (ECC) is emerging as an attractive approach to public-key cryptography for constrained environments, because of the small key sizes and computational efficiency, while preserving the same security level as the standard methods. The performance of public-key cryptography methods is critical in embedded environments such as applications for...

    Provided By University of Siegen