University of Wisconsin System

Displaying 1-27 of 27 results

  • White Papers // Mar 2011

    Real-Time GPU-Based Voxelization and Applications

    This paper proposes a new real-time voxelization algorithm using newly available GPU functionalities. The voxelization algorithm is efficient and able to real-time trans-form a highly complex surface-represented scene into a set of high-resolution voxels in only one GPU pass using the newly available geometry shader. The usage of 3D texture...

    Provided By University of Wisconsin System

  • White Papers // Mar 2011

    Defective Error/Pointer Interactions in the Linux Kernel

    Linux run-time errors are represented by integer values referred to as error codes. These values propagate across long function-call chains before being handled. As these error codes propagate, they are often temporarily or permanently encoded into pointer values. Error-valued pointers are not valid memory addresses, and therefore require special care...

    Provided By University of Wisconsin System

  • White Papers // Feb 2011

    EPIC: Platform-as-a-Service Model for Cloud Networking

    Enterprises today face several challenges when hosting line-of-business applications in the cloud. Central too many of these challenges is the limited support for control over cloud network functions, such as, the ability to ensure security, performance guarantees or isolation, and to flexibly interpose middleboxes in application deployments. In this paper,...

    Provided By University of Wisconsin System

  • White Papers // Jan 2011

    OpenSPLySER: The Integrated OpenSPARC and DySER Design

    The Dynamically Synthesized Execution (DySE) model has been proposed to improve the energy efficiency and performance of general purpose programmable processors. The authors describe how a DySE Resource (DySER) block can be integrated into a processor pipeline. The block size can be adjusted based on design constraints, but they integrate...

    Provided By University of Wisconsin System

  • White Papers // Dec 2010

    CPU Futures: Scheduler Support for Application Management of CPU Contention

    The authors introduce CPU Futures, a system designed to enable application control of scheduling for server workloads, even during system overload. CPU Futures contains two novel components: an in-kernel herald that anticipates application CPU performance degradation and a user-level feedback controller that responds to these predictions on behalf of the...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    H-1B Processing Procedures

    This paper is a guide to obtaining H-1B status for employees of University of Wisconsin - Madison Departments. The hiring Department must complete the three step process for the H-1B petition as described in this packet. This information will assist Departments in completing the necessary paperwork to obtain H-1B status...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Design and Evaluation of Dynamically Specialized Datapaths With the DySER Architecture

    Due to limits in technology scaling, energy efficiency of logic devices is decreasing in successive generations. To provide continued performance improvements without increasing power, regardless of the sequential or parallel nature of the application, Microarchitectural energy efficiency must improve. The authors propose Dynamically Specialized Execution to improve the energy efficiency...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Valid Inequalities for the Pooling Problem With Binary Variables

    The pooling problem consists of finding the optimal quantity of final products to obtain by blending different compositions of raw materials in pools. Bilinear terms are required to model the quality of products in the pools, making the pooling problem a non-convex continuous optimization problem. In this paper the authors...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Effective Separation of Disjunctive Cuts for Convex Mixed Integer Nonlinear Programs

    The authors describe a computationally effective method for generating disjunctive inequalities for convex Mixed-Integer NonLinear Programs (MINLPs). The method relies on solving a sequence of cut-generating linear programs, and in the limit will generate an inequality as strong as can be produced by the cut-generating nonlinear program suggested by Stubbs...

    Provided By University of Wisconsin System

  • White Papers // Oct 2010

    Karma: Scalable Deterministic Record-Replay

    Recent research in deterministic record-replay seeks to ease debugging, security, and fault tolerance on otherwise nondeterministic multicore systems. The important challenge of handling shared memory races (that can occur on any memory reference) can be made more efficient with hardware support. Recent proposals record how long threads run in isolation...

    Provided By University of Wisconsin System

  • White Papers // Oct 2010

    Handheld Vs. Non-Handheld Traffic: Implications for Campus WiFi Networks

    Smartphones, portable music players, and other handheld devices have become a major computing platform. Wherever users go, they utilize 3G and WiFi connectivity to access a wide array of Internet services. The small, mobile nature of these devices results in a uniquemix of application and network usage. As more handheld...

    Provided By University of Wisconsin System

  • White Papers // Jul 2010

    InfoNames: An Information-Based Naming Scheme for Multimedia Content

    Recent proposals have argued for data-centric mechanisms that decouple data delivery from the sources of the data and the transfer protocols. The authors take this idea to its logical completion and argue for enabling content distribution schemes to name and query directly for the underlying information. The motivation for this...

    Provided By University of Wisconsin System

  • White Papers // Jun 2010

    SIP: Speculative Insertion Policy for High Performance Caching

    High performance cache mechanisms have a great impact on overall performance of computer systems by reducing memory-access latency. Least-Recently Used (LRU) mechanism can achieve good performance in small workload; however, it suffers from thrashing caused by memory-intensive application. To address this challenge, dynamic insertion policy-DIP, which dynamically switches between LRU...

    Provided By University of Wisconsin System

  • White Papers // Apr 2010

    The Design, Modeling, and Evaluation of the Relax Architectural Framework

    As transistor technology scales ever further, hardware reliability is becoming harder to manage. The effects of soft errors, variability, wear-out, and yield are intensifying to the point where it becomes difficult to harness the benefits of deeper scaling without mechanisms for hardware fault detection and correction. The authors observe that...

    Provided By University of Wisconsin System

  • White Papers // Mar 2010

    Revisiting Database Storage Optimizations on Flash

    The database storage hierarchy has been heavily optimized for the performance characteristics of disks. Storage managers typically employ row- or column-oriented storage layouts, or a combination, to improve the I/O performance of different query workloads with disks. The recent rise of flash memory-based Solid-State Drives (SSDs) significantly change the performance...

    Provided By University of Wisconsin System

  • White Papers // Mar 2010

    On Energy Management, Load Balancing and Replication

    Energy consumption is a crucial and rising operational cost for data-intensive computing. In this paper the authors investigate some opportunities and challenges that arise in energy-aware computing in a cluster of servers running data-intensive workloads. A key insight is that in most data centers, servers are underutilized, which makes it...

    Provided By University of Wisconsin System

  • White Papers // Feb 2010

    Directed Proof Generation for Machine Code

    The authors present the algorithms used in MCVETO (Machine-Code VErification TOol), a tool to check whether a stripped machinecode program satisfies a safety property. The verification problem that MCVETO addresses is challenging because it cannot assume that it has access to certain structures commonly relied on by source-code verification tools,...

    Provided By University of Wisconsin System

  • White Papers // Feb 2010

    BCE: Extracting Botnet Commands From Bot Executables

    Botnets are a major threat to the security of computer systems and the Internet. An increasing number of individual Internet sites have been compromised by attacks from all across the world to become part of various kinds of malicious botnets. The Internet security research community has made significant efforts to...

    Provided By University of Wisconsin System

  • White Papers // Oct 2009

    Algorithms and Software for Convex Mixed Integer Nonlinear Programs

    This paper provides a survey of recent progress and software for solving Mixed Integer NonLinear Programs (MINLP) wherein the objective and constraints are defined by convex functions and integrality restrictions are imposed on a subset of the decision variables. Convex MINLPs have received sustained attention in very years. By exploiting...

    Provided By University of Wisconsin System

  • White Papers // Sep 2009

    Solving Large Steiner Triple Covering Problems

    Computing the 1-width of the incidence matrix of a Steiner Triple System gives rise to small set covering instances that provide a computational challenge for integer programming techniques. One major source of difficulty for instances of this family is their highly symmetric structure, which impairs the performance of most branch-and-bound...

    Provided By University of Wisconsin System

  • White Papers // Sep 2009

    Forwardflow: Scalable, RAM-Based Dataflow Execution

    Power (and thermal) limits have forced an industry-wide shift from increasingly complex uniprocessors to multicore chips with 4, 8, and even 16 simpler processor cores. Yet Amdahl's Law suggests that these cores should not be too simple, lest they exacerbate even a parallel application's sequential bottlenecks. Furthermore, running all cores...

    Provided By University of Wisconsin System

  • White Papers // Aug 2009

    Whatever it is, you can get it on the Internet: Toward an Information-Based Network Architecture

    Recent suggestions for content-centric networking propose naming content directly and to resolve a content name to host locations. Content can then be served from any host holding it. The authors take naming and content delivery to the next logical level. They propose an information-based network architecture based on naming and...

    Provided By University of Wisconsin System

  • White Papers // Jun 2009

    MCDASH: Refinement-Based Property Verification for Machine Code

    This paper presents MCDASH, a refinement-based model checker for machine code. While model checkers such as SLAM, BLAST, and DASH have each made significant contributions in the field of verification/flaw-detection, their use has been restricted to programs for which source code is available. This paper discusses several challenges that arise...

    Provided By University of Wisconsin System

  • White Papers // Apr 2009

    RouteBazaar: An Economic Framework for Flexible Routing

    The Internet's routing protocol provides users a single end-to-end route that is not guaranteed to be available or to meet user requirements. The paper addresses this rigidity using an economically grounded approach that appeals both to users and to service providers. They propose a framework called RouteBazaar in which service...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    To CMP or Not to CMP: Analyzing Packet Classification on Modern and Traditional Parallel Architectures

    Packet classification is a central component of modern network functionality, yet satisfactory memory usage and overall performance remains an elusive challenge at the highest speeds. The recent emergence of chip multiprocessors and other low-cost, highly parallel processing hardware provides a promising platform on which to realize increased classification performance. In...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    Building Cheap and Large CAMs Using BufferHash

    The authors show how to build cheap and large CAMs, or CLAMs, using flash memory. These CLAMs are targeted at an emerging class of networking applications that require massive indexes running into a hundred GB or more, with items been inserted, updated and looked up at a rapid rate. Examples...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    On the Effectiveness of Pre-Acceptance Spam Filterning

    Modern SMTP servers apply a variety of mechanisms to stem the volume of spam delivered to users. These techniques can be broadly classified into two categories: pre-acceptance approaches, which apply prior to a message being accepted (e.g blacklisting and whitelisting), and post-acceptance techniques which apply after a message has been...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    H-1B Processing Procedures

    This paper is a guide to obtaining H-1B status for employees of University of Wisconsin - Madison Departments. The hiring Department must complete the three step process for the H-1B petition as described in this packet. This information will assist Departments in completing the necessary paperwork to obtain H-1B status...

    Provided By University of Wisconsin System

  • White Papers // Aug 2009

    Whatever it is, you can get it on the Internet: Toward an Information-Based Network Architecture

    Recent suggestions for content-centric networking propose naming content directly and to resolve a content name to host locations. Content can then be served from any host holding it. The authors take naming and content delivery to the next logical level. They propose an information-based network architecture based on naming and...

    Provided By University of Wisconsin System

  • White Papers // Dec 2010

    CPU Futures: Scheduler Support for Application Management of CPU Contention

    The authors introduce CPU Futures, a system designed to enable application control of scheduling for server workloads, even during system overload. CPU Futures contains two novel components: an in-kernel herald that anticipates application CPU performance degradation and a user-level feedback controller that responds to these predictions on behalf of the...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Design and Evaluation of Dynamically Specialized Datapaths With the DySER Architecture

    Due to limits in technology scaling, energy efficiency of logic devices is decreasing in successive generations. To provide continued performance improvements without increasing power, regardless of the sequential or parallel nature of the application, Microarchitectural energy efficiency must improve. The authors propose Dynamically Specialized Execution to improve the energy efficiency...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Valid Inequalities for the Pooling Problem With Binary Variables

    The pooling problem consists of finding the optimal quantity of final products to obtain by blending different compositions of raw materials in pools. Bilinear terms are required to model the quality of products in the pools, making the pooling problem a non-convex continuous optimization problem. In this paper the authors...

    Provided By University of Wisconsin System

  • White Papers // Nov 2010

    Effective Separation of Disjunctive Cuts for Convex Mixed Integer Nonlinear Programs

    The authors describe a computationally effective method for generating disjunctive inequalities for convex Mixed-Integer NonLinear Programs (MINLPs). The method relies on solving a sequence of cut-generating linear programs, and in the limit will generate an inequality as strong as can be produced by the cut-generating nonlinear program suggested by Stubbs...

    Provided By University of Wisconsin System

  • White Papers // Oct 2010

    Karma: Scalable Deterministic Record-Replay

    Recent research in deterministic record-replay seeks to ease debugging, security, and fault tolerance on otherwise nondeterministic multicore systems. The important challenge of handling shared memory races (that can occur on any memory reference) can be made more efficient with hardware support. Recent proposals record how long threads run in isolation...

    Provided By University of Wisconsin System

  • White Papers // Oct 2010

    Handheld Vs. Non-Handheld Traffic: Implications for Campus WiFi Networks

    Smartphones, portable music players, and other handheld devices have become a major computing platform. Wherever users go, they utilize 3G and WiFi connectivity to access a wide array of Internet services. The small, mobile nature of these devices results in a uniquemix of application and network usage. As more handheld...

    Provided By University of Wisconsin System

  • White Papers // Jul 2010

    InfoNames: An Information-Based Naming Scheme for Multimedia Content

    Recent proposals have argued for data-centric mechanisms that decouple data delivery from the sources of the data and the transfer protocols. The authors take this idea to its logical completion and argue for enabling content distribution schemes to name and query directly for the underlying information. The motivation for this...

    Provided By University of Wisconsin System

  • White Papers // Jun 2010

    SIP: Speculative Insertion Policy for High Performance Caching

    High performance cache mechanisms have a great impact on overall performance of computer systems by reducing memory-access latency. Least-Recently Used (LRU) mechanism can achieve good performance in small workload; however, it suffers from thrashing caused by memory-intensive application. To address this challenge, dynamic insertion policy-DIP, which dynamically switches between LRU...

    Provided By University of Wisconsin System

  • White Papers // Apr 2010

    The Design, Modeling, and Evaluation of the Relax Architectural Framework

    As transistor technology scales ever further, hardware reliability is becoming harder to manage. The effects of soft errors, variability, wear-out, and yield are intensifying to the point where it becomes difficult to harness the benefits of deeper scaling without mechanisms for hardware fault detection and correction. The authors observe that...

    Provided By University of Wisconsin System

  • White Papers // Mar 2010

    Revisiting Database Storage Optimizations on Flash

    The database storage hierarchy has been heavily optimized for the performance characteristics of disks. Storage managers typically employ row- or column-oriented storage layouts, or a combination, to improve the I/O performance of different query workloads with disks. The recent rise of flash memory-based Solid-State Drives (SSDs) significantly change the performance...

    Provided By University of Wisconsin System

  • White Papers // Mar 2010

    On Energy Management, Load Balancing and Replication

    Energy consumption is a crucial and rising operational cost for data-intensive computing. In this paper the authors investigate some opportunities and challenges that arise in energy-aware computing in a cluster of servers running data-intensive workloads. A key insight is that in most data centers, servers are underutilized, which makes it...

    Provided By University of Wisconsin System

  • White Papers // Feb 2010

    Directed Proof Generation for Machine Code

    The authors present the algorithms used in MCVETO (Machine-Code VErification TOol), a tool to check whether a stripped machinecode program satisfies a safety property. The verification problem that MCVETO addresses is challenging because it cannot assume that it has access to certain structures commonly relied on by source-code verification tools,...

    Provided By University of Wisconsin System

  • White Papers // Feb 2010

    BCE: Extracting Botnet Commands From Bot Executables

    Botnets are a major threat to the security of computer systems and the Internet. An increasing number of individual Internet sites have been compromised by attacks from all across the world to become part of various kinds of malicious botnets. The Internet security research community has made significant efforts to...

    Provided By University of Wisconsin System

  • White Papers // Oct 2009

    Algorithms and Software for Convex Mixed Integer Nonlinear Programs

    This paper provides a survey of recent progress and software for solving Mixed Integer NonLinear Programs (MINLP) wherein the objective and constraints are defined by convex functions and integrality restrictions are imposed on a subset of the decision variables. Convex MINLPs have received sustained attention in very years. By exploiting...

    Provided By University of Wisconsin System

  • White Papers // Sep 2009

    Solving Large Steiner Triple Covering Problems

    Computing the 1-width of the incidence matrix of a Steiner Triple System gives rise to small set covering instances that provide a computational challenge for integer programming techniques. One major source of difficulty for instances of this family is their highly symmetric structure, which impairs the performance of most branch-and-bound...

    Provided By University of Wisconsin System

  • White Papers // Jun 2009

    MCDASH: Refinement-Based Property Verification for Machine Code

    This paper presents MCDASH, a refinement-based model checker for machine code. While model checkers such as SLAM, BLAST, and DASH have each made significant contributions in the field of verification/flaw-detection, their use has been restricted to programs for which source code is available. This paper discusses several challenges that arise...

    Provided By University of Wisconsin System

  • White Papers // Sep 2009

    Forwardflow: Scalable, RAM-Based Dataflow Execution

    Power (and thermal) limits have forced an industry-wide shift from increasingly complex uniprocessors to multicore chips with 4, 8, and even 16 simpler processor cores. Yet Amdahl's Law suggests that these cores should not be too simple, lest they exacerbate even a parallel application's sequential bottlenecks. Furthermore, running all cores...

    Provided By University of Wisconsin System

  • White Papers // Apr 2009

    RouteBazaar: An Economic Framework for Flexible Routing

    The Internet's routing protocol provides users a single end-to-end route that is not guaranteed to be available or to meet user requirements. The paper addresses this rigidity using an economically grounded approach that appeals both to users and to service providers. They propose a framework called RouteBazaar in which service...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    To CMP or Not to CMP: Analyzing Packet Classification on Modern and Traditional Parallel Architectures

    Packet classification is a central component of modern network functionality, yet satisfactory memory usage and overall performance remains an elusive challenge at the highest speeds. The recent emergence of chip multiprocessors and other low-cost, highly parallel processing hardware provides a promising platform on which to realize increased classification performance. In...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    Building Cheap and Large CAMs Using BufferHash

    The authors show how to build cheap and large CAMs, or CLAMs, using flash memory. These CLAMs are targeted at an emerging class of networking applications that require massive indexes running into a hundred GB or more, with items been inserted, updated and looked up at a rapid rate. Examples...

    Provided By University of Wisconsin System

  • White Papers // Feb 2009

    On the Effectiveness of Pre-Acceptance Spam Filterning

    Modern SMTP servers apply a variety of mechanisms to stem the volume of spam delivered to users. These techniques can be broadly classified into two categories: pre-acceptance approaches, which apply prior to a message being accepted (e.g blacklisting and whitelisting), and post-acceptance techniques which apply after a message has been...

    Provided By University of Wisconsin System

  • White Papers // Mar 2011

    Real-Time GPU-Based Voxelization and Applications

    This paper proposes a new real-time voxelization algorithm using newly available GPU functionalities. The voxelization algorithm is efficient and able to real-time trans-form a highly complex surface-represented scene into a set of high-resolution voxels in only one GPU pass using the newly available geometry shader. The usage of 3D texture...

    Provided By University of Wisconsin System

  • White Papers // Mar 2011

    Defective Error/Pointer Interactions in the Linux Kernel

    Linux run-time errors are represented by integer values referred to as error codes. These values propagate across long function-call chains before being handled. As these error codes propagate, they are often temporarily or permanently encoded into pointer values. Error-valued pointers are not valid memory addresses, and therefore require special care...

    Provided By University of Wisconsin System

  • White Papers // Feb 2011

    EPIC: Platform-as-a-Service Model for Cloud Networking

    Enterprises today face several challenges when hosting line-of-business applications in the cloud. Central too many of these challenges is the limited support for control over cloud network functions, such as, the ability to ensure security, performance guarantees or isolation, and to flexibly interpose middleboxes in application deployments. In this paper,...

    Provided By University of Wisconsin System

  • White Papers // Jan 2011

    OpenSPLySER: The Integrated OpenSPARC and DySER Design

    The Dynamically Synthesized Execution (DySE) model has been proposed to improve the energy efficiency and performance of general purpose programmable processors. The authors describe how a DySE Resource (DySER) block can be integrated into a processor pipeline. The block size can be adjusted based on design constraints, but they integrate...

    Provided By University of Wisconsin System