Hardware

Stay current with the components, peripherals and physical parts that constitute your IT department.

  • White Papers // Jan 2011

    Frugal but Flexible Multicore Topologies in Support of Resource Variation-Driven Adaptivity

    Given the projected higher variations in the availability of computational resources, adaptive static schedules have been developed to attain high-speed execution reconfiguration with no reliance on any runtime rescheduling decisions. These schedules are able to deliver predictable execution despite the increased levels of device unreliability in future multicore systems. Yet...

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  • White Papers // Jan 2011

    Targeting Code Diversity with Run-time Adjustable Issue-slots in a Chip Multiprocessor

    This paper presents an adaptable soft-core Chip Multi-Processor (CMP). The processor Instruction Set Architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be adjusted at run-time (before an application starts). The processor has eight 2-issue cores that can run independently from each other. If not...

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  • White Papers // Jan 2011

    MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers

    The authors describe a parameterized memory system suitable as target for automatic high-level language to hardware compilers for reconfigurable computers. It fully supports the spatial computation paradigm by allowing the realization of each memory operator by a dedicated hardware memory port. Interport coherency is maintained only for those ports that...

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  • White Papers // Jan 2011

    I2CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics

    Integrating Coarse-Grained Reconfigurable Architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without explicit design space exploration. In this paper, the authors present a novel methodology for incremental...

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  • White Papers // Jan 2011

    Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis

    The authors present HYBRO, an automatic methodology to generate high coverage input vectors for Register Transfer Level (RTL) designs based on branch-coverage directed approach. HYBRO uses dynamic simulation data and static analysis of RTL Control Flow Graphs (CFGs). A concrete simulation is applied over a fixed number of cycles. Instrumented...

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  • White Papers // Jan 2011

    RON: An On-Chip Ring Oscillator Network for Hardware Trojan Detection

    Integrated Circuits (ICs) are becoming increasingly vulnerable to malicious alterations, referred to as hardware Trojans. Detection of these inclusions is of utmost importance, as they may potentially be inserted into ICs bound for military, financial, or other critical applications. A novel on-chip structure including a Ring Oscillator Network (RON), distributed...

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  • White Papers // Jan 2011

    Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models

    Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper describes a radically different approach to gate-level simulation based on a concept of temporal rather than conventional spatial...

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  • White Papers // Jan 2011

    A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

    The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. The authors propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar...

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  • White Papers // Jan 2011

    Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks

    Modern security-aware embedded systems need protection against fault attacks. These attacks rely on intentionally induced faults. Such intentional faults have not only a different origin, but also a different nature than errors that fault-tolerant systems usually have to face. For instance an adversary who attacks the circuit with two lasers...

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  • White Papers // Jan 2011

    Priority Division: A High-Speed Shared-Memory Bus Arbitration With Bounded Latency

    In state-of-the-art Multi-Processor Systems-on-Chip (MPSoC), interconnect of processing elements has a major impact on the system's overall average-case and worst-case performance. Moreover, in real-time applications predictability of inter-chip communication latency is imperative for bounding the response time of the overall system. In shared-memory MPSoCs buses are still the prevalent means...

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  • White Papers // Jan 2011

    Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling

    New tendencies envisage 3D Multi-Processor System-on-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation High-Performance Computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs, supplying electrical power to the computing equipment and constantly removing the...

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  • White Papers // Jan 2011

    Abstract State Machines as an Intermediate Representation for High-Level Synthesis

    This paper presents a high-level synthesis methodology that uses the Abstract State Machines (ASMs) formalism as an Intermediate Representation (IR). The authors perform scheduling and allocation on this IR, and generate synthesizable VHDL. They have the following advantages when using ASMs as an IR: it allows the specification of both...

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  • White Papers // Jan 2011

    Intermediate Representations for Controllers in Chip Generators

    Creating parameterized \"Chip generators\" has been proposed as one way to decrease chip NRE costs. While many approaches are available for creating or generating flexible data path elements, the design of flexible controllers is more problematic. The most common approach is to create a micro-coded engine as the controller, which...

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  • White Papers // Jan 2011

    Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

    This paper introduces the first available tool flow for dynamic partial reconfiguration on the Spartan-6 family. In addition, the paper proposes a new configuration method called Fast Start-up targeting modern FPGA architectures, where the FPGA is configured in two-steps, instead of using a single (monolithic) full device configuration. In this...

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  • White Papers // Jan 2011

    Timing Variation-Aware Custom Instruction Extension Technique

    In this paper, the authors propose a technique for Custom Instruction (CI) extension considering process variations. It bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In the proposed method, instead of using the conventional Static Timing Analysis (STA), Statistical Static Timing analysis (SSTA)...

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  • White Papers // Jan 2011

    A UML 2-based Hardware-Software Co-Design Framework for Body Sensor Network Applications

    This paper proposes a unified framework for the hardware/software co-design of body sensor network applications that aims to enhance both modularity and reusability. The proposed framework consists of a Unified Modeling Language (UML) 2 profile for TinyOS applications and a corresponding simulator. The UML profile allows for the description of...

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  • White Papers // Jan 2011

    Resynchronization of Cyclo-Static Dataflow Graphs

    Parallel stream processing applications are often executed on shared-memory multiprocessor systems. Synchronization between tasks is needed to guarantee correct functional behavior. An increase in the communication granularity of the tasks in the parallel application can decrease the synchronization overhead. However using coarser-grained synchronization can result in deadlock or violation of...

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  • White Papers // Jan 2011

    A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores

    High-end multicore processors are characterized by high power density with significant spatial and temporal variability. This leads to power and temperature hot-spots, which may cause non-uniform ageing and accelerated chip failure. These critical issues can be tackled on-line by closed-loop thermal and reliability management policies. Model Predictive Controllers (MPC) outperform...

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  • White Papers // Jan 2011

    Composing Heterogeneous Components for System-Wide Performance Analysis

    Component-based validation techniques for parallel and distributed embedded systems should be able to deal with heterogeneous components, interactions, and specification mechanisms. This paper describes various approaches that allow the composition of subsystems with different execution and interaction semantics by combining computational and analytic models. In particular, this work shows how...

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  • White Papers // Jan 2011

    Controlled Timing-Error Acceptance for Low Energy IDCT Design

    In embedded Digital Signal Processing (DSP) systems, quality is set by a Signal-to-Noise Ratio (SNR) floor. Conventional digital design strategies guarantee timing correctness of all operations, which leaves large quality margins in practical systems and sacrifices energy efficiency. This paper presents techniques to significantly improve energy efficiency by shaping the...

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  • White Papers // Jan 2011

    Using Contract-based Component Specifications for Virtual Integration Testing and Architecture Design

    The authors elaborate on the theoretical foundation and practical application of the contract-based specification method originally developed in the integrated project SPEEDS for two key use cases in embedded systems design. They demonstrate how formal contract-based component specifications for functional, safety, and real-time aspects of components can be expressed using...

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  • White Papers // Jan 2011

    The Potential of Reconfigurable Hardware for HPC Cryptanalysis of SHA-1

    Modern reconfigurable technologies can have a number of inherent advantages for cryptanalytic applications. Aimed at the cryptanalysis of the SHA-1 hash function, this work explores this potential showing new approaches inherently based on hardware re-configurability, enabling algorithm and architecture exploration, input-dependent system specialization, and low-level optimizations based on static/dynamic reconfiguration....

    Provided By edaa

  • White Papers // Jan 2011

    Early Chip Planning Cockpit

    The design of high-performance servers has always been a challenging art. Now, server designers are being asked to explore a much larger design space as they consider multicore heterogeneous architecture and the limits of advancing silicon technology. Bringing automation to the early stages of design can enable more rapid and...

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  • White Papers // Jan 2011

    SoC Infrastructures for Predictable System Integration

    Advanced SoCs integrate a diverse set of system functions that pose different requirements on the SoC infrastructure. Predictable integration of such SoCs, with guaranteed Quality-of-Service (QoS) for the real-time functions, is becoming increasingly challenging. The authors present a structured approach to predictable integration based on a combination of architectural principles...

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  • White Papers // Jan 2011

    Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives

    The authors present a runtime system that uses the explicit on-chip communication mechanisms of the SARC multi-core architecture, to implement efficiently the OpenMP programming model and enable the exploitation of fine-grain parallelism in OpenMP programs. They explore the design space of implementation of OpenMP directives and runtime intrinsics, using a...

    Provided By edaa

  • White Papers // Jan 2011

    Precise WCET Calculation in Highly Variant Real-Time Systems

    Embedded hard real-time systems that are based on software product lines using dynamically derivable variants are prone to overestimations in static WCET analyses. This is due to the fact that infeasible paths in the code resulting from infeasible variant combinations are unknown to the analysis. This paper presents an approach...

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  • White Papers // Jan 2011

    Scratchpad Memory Optimizations for Digital Signal Processing Applications

    Modern Digital Signal Processors (DSPs) need to support a diverse array of applications ranging from digital filters to video decoding. Many of these applications have drastically different precision and on-chip memory requirements. Moreover, DSPs often employ aggressive Dynamic Voltage and Frequency Scaling (DVFS) techniques to minimize power consumption. However, at...

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  • White Papers // Jan 2011

    Power Management Verification Experiences in Wireless SoCs

    The authors look into the validation a power managed ARM Cortex A-8 core used in SoCs targeted for mobile segment. Low power design techniques used on the chip include clock gating, voltage scaling, and power gating. They focus on the verification challenges faced in designing the processor core including RTL...

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  • White Papers // Jan 2011

    Gemma in April: A Matrix-like Parallel Programming Architecture on OpenCL

    Now-a-days, Graphics Processing Unit (GPU), as a kind of massive parallel processor, has been widely used in general purposed computing tasks. Although there have been mature development tools, it is not a trivial task for programmers to write GPU programs. Based on this consideration, the authors propose a novel parallel...

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  • White Papers // Jan 2011

    Evaluating the Potential of Graphics Processors for High Performance Embedded Computing

    Today's high performance embedded computing applications are posing significant challenges for processing throughout. Traditionally, such applications have been realized on Application Specific Integrated Circuits (ASICs) and/or Digital Signal Processors (DSP). However, ASICs' advantage in performance and power often could not justify the fast increasing fabrication cost, while current DSP offers...

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  • White Papers // Jan 2011

    FARM: Fault-Aware Resource Management in NoC-Based Multiprocessor Platforms

    In this paper, the authors address the problem of run-time resource management in non-ideal multiprocessor platforms where communication happens via the Network-on-Chip (NoCs) approach. More precisely, they propose a system-level fault-tolerant technique for application mapping which aims at optimizing the entire system performance and communication energy consumption, while considering the...

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  • White Papers // Jan 2011

    Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems

    Many applications contain loops with an undetermined number of iterations. These loops have to be parallelized in order to increase the throughput when executed on an embedded multiprocessor platform. This paper presents a method to automatically extract a parallel task graph based on function level parallelism from a sequential nested...

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  • White Papers // Jan 2011

    Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture

    On-chip interconnection networks are rapidly becoming the reference communication fabric for multi-core computing platforms both in high-performance processors and in many embedded systems. As the integration densities and the uncertainties in the manufacturing process keep increasing, complementing NoCs with efficient test mechanisms becomes a key requirement to cope with high...

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  • White Papers // Jan 2011

    ReliNoC: A Reliable Network for Priority-Based On-Chip Communication

    The reliability of Networks-on-Chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. The authors propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Their network leverages a dual physical channel...

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  • White Papers // Jan 2011

    Virtual Manycore Platforms: Moving Towards 100+ Processor Cores

    The evolution to Manycore platforms is real, both in the High-Performance Computing domain and in embedded systems. If the authors start with ten or more cores, they can see the evolution to many tens of cores and to platforms with 100 or more occurring in the next few years. These...

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  • White Papers // Jan 2011

    Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip

    The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology in current System-on-Chips (SoCs) for integrating a large number of processing elements in a single die. It has the advantage of enhanced performance, scalability and modularity, compared with previous bus-based communication architectures. Recently, a new Triplet-based Hierarchical Interconnection Network (THIN)...

    Provided By edaa

  • White Papers // Jan 2011

    Timing-Constrained I/O Buffer Placement for Flip-Chip Designs

    With the increase of circuit complexity and the decrease of feature size, the dramatic demand for I/O counts becomes a significant issue in VLSI designs. Due to inappropriate assignment of bump pads or improper placement of I/O buffers, the configured delays of I/O signals may not satisfy the timing requirement...

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  • White Papers // Jan 2011

    Flow-Based Partitioning and Position Constraints in VLSI Placement

    In this paper, the authors present a new quadratic, partitioning-based placement algorithm which is able to handle non-convex and overlapping position constraints to subsets of cells, the movebounds. Their new Flow-Based Partitioning (FBP) combines a global MinCostFlow model for computing directions with extremely fast and highly parallelizable local realization steps....

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  • White Papers // Jan 2011

    NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs

    For many embedded systems, data protection is becoming a major issue. On those systems, processors are often heterogeneous and prevent from deploying a common, trusted hypervisor on all of them. Multiple native software stacks are thus bound to share the resources without protection between them. NoC-MPU is a Memory Protection...

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  • White Papers // Jan 2011

    Architectural Exploration of 3D FPGas Towards a Better Balance Between Area and Delay

    The emerging 3D technology, which stacks multiple dies within a single chip and utilizes Through-Silicon Vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA architecture can evolve into a 3D one by extending its signal switching scheme...

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