Processors
Chips are everywhere -- in your PCs, laptops, servers, cars and every gadget you can think of -- and the processor market is shifting as the mobile market grows.
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The Ultimate HPC Cluster Development Suite
Intel® Cluster Studio XE 2013 SP1 can help you achieve top application performance for Intel® Xeon® processor and Intel® Xeon Phi ™ coprocessor-based systems. The suite provides a comprehensive set of standards-driven C, C++, and Fortran development tools and programming models to enable developers to efficiently develop, analyze, and optimize...
Sponsored By Intel Software
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TrC-MC: Decentralized Software Transactional Memory for Multi-Multicore Computers
To achieve single-lock atomicity in software transactional memory systems, the commit procedure often goes through a common clock variable. When there are frequent transactional commits, clock sharing becomes inefficient. Tremendous cache contention takes place between the processors and the computing throughput no longer scales with processor count. Therefore, traditional transactional...
Provided By Institute of Electrical and Electronics Engineers
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Directory-Oblivious Capacity Sharing in Tiled CMPs
In bus-based CMPs with private caches, Capacity Sharing is applied by spilling victim cache blocks from over-utilized caches to under-utilized ones. If a spilled block is needed, it can be retrieved by posting a miss on the bus. Prior work in this domain focused on Capacity Sharing design and put...
Provided By North Carolina State University
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Study of Arm Based Temperature Measurement and Control System Using CPLD
In this paper a temperature measurement and control system is proposed using ARM processor S3C2440 as a controlling device. This system uses LM35D sensor and its related peripherals for temperature measurement. This temperature is filtered and transmitted to the ADC MCP3201. ARM and CPLD are used for processing and controlling...
Provided By IOSR Journal of Engineering
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Pen Drive to Pen Drive and Mobile Data Transfer Using ARM
Generally, the authors used to transfer data between two pen drives by using laptops or desktops. But it is not always possible to carry such a large size device to the particular location. So to overcome this problem, they are designing a hardware which is more compact to carry anywhere....
Provided By IOSR Journal of Engineering
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Embedded Ethernet Interface Using Arm Processor
Currently device with microcontroller has been widely used in industrial field. However, a large number of devices don't have the network interface and the data from them cannot be transmitted in network. A design of ARM processor-based embedded Ethernet interface is presented. In the design, an existing SPI serial device...
Provided By IOSR Journal of Engineering
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Scheduling Simulations: An Experimental Approach to Time-Sharing Multiprocessor Scheduling Schemes
Real time systems that are logically programmed for scientific applications involve frequent job arrivals, thus requires a parallel architecture, so that maximum applications can be executed simultaneously resulting in less waiting time and maximum resource utilization. This must be achieved by workload partitioning & characterization, directs towards the development of...
Provided By International Journal of Computer Applications
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Design and Implementation of Soft Core Processor on FPGA Based on Avalon Bus and SOPC Technology
Nios II is a soft Processor that can be incorporated in system implemented on a FPGA device by using Avalon Interface & SOPC technology. It allows easy interfacing of new peripheral blocks to existing software. The FPGA has the capability of parallel processing and hardware modification. It offers the possibility...
Provided By International Journal of Computer Applications
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Flexible Capacity Partitioning in Many-Core Tiled CMPs
Chip Multi-Processors (CMP) have become a mainstream computing platform. As transistor density shrinks and the number of cores increases, more scalable CMP architectures will emerge. Recently, tiled architectures have shown such scalable characteristics and been used in many industry chips. The memory hierarchy in tiled architectures presents interesting design challenges....
Provided By North Carolina State University
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A Flexible Real-Time Locking Protocol for Multiprocessors
Real-time scheduling algorithms for multiprocessor systems have been the subject of considerable recent interest. For such an algorithm to be truly useful in practice, support for semaphore-based locking must be provided. However, for many global scheduling algorithms, no such mechanisms have been proposed. Furthermore, in the partitioned case, most prior...
Provided By University of North Alabama
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Feather-Trace: A Light-Weight Event Tracing Toolkit
The authors present a light-weight event tracing toolkit for real-time operating systems on the Intel x86 platform. Their approach is wait-free, multiprocessor-safe, and introduces very low overhead. Only a single unconditional jump instruction is required to distinguish between enabled and disabled events. As a case study, they traced the locking...
Provided By University of North Alabama
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Integrating Hard/Soft Real-Time Tasks and Best-Effort Jobs on Multiprocessors
An important trend in computing is the ongoing move towards system- and chip-level parallelism. Because of heat and power issues, it has become increasingly difficult to improve processor performance by increasing clock speeds. Therefore, in order to continue performance improvements, major processor manufacturers, such as Intel, AMD, IBM, and Sun...
Provided By University of North Alabama
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Schedulability Analysis of Distributed Real-Time applications Under Dependence and Several Latency Constraints
In this paper, the authors focus on the analysis of real-time non preemptive multiprocessor scheduling with precedence and several latency constraints. It aims to specify a schedulability condition which enables a designer to check a priori -without executing or simulating-if its scheduling of tasks will hold the precedence between tasks...
Provided By International Journal of Computer Applications
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Parallel Gauss-Seidel On A Torus Network-On-Chip Architecture
Computing problems from the scientific and engineering fields are getting more and more complex requiring large memory capacity and high computational speed. One way of matching these needs is by using parallel computing systems with a large number of processors. Network-on-Chip multicore architectures with a large number of processing elements...
Provided By World Science Festival
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Performance Evaluation of FPM on Spartan Family FPGas and Analyze Its Effect on Bonded IOBs
VHDL programming for IEEE single precision floating point multiplier module have been explored because floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that...
Provided By International Journal of Electronics Communication and Computer Engineering
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Energy-Efficient Interconnect Via Router Parking
The increase in on-chip core counts in Chip MultiProcessors (CMPs) has led to the adoption of interconnects such as Mesh and Torus, which consume an increasing fraction of the chip power. Moreover, as technology and voltage continue to scale down, static power consumes a larger fraction of the total power;...
Provided By Intel
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DCT & DWT Images Compression Algorithms in Wireless Sensors Networks: Comparative Study and Performance Analysis
The recent availability of inexpensive hardware has enabled the new research field of wireless sensor networks. This is a network of interconnected devices, capable of retrieving images from the environment. The nodes, in this type of network, have very limited resources, in terms of processing unit, bandwidth and energy. Efficient...
Provided By AIRCC
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Improving Throughput of RC4 Algorithm Using Multithreading Techniques in Multicore Processors
RC4 is the most widely used stream cipher around. So, it is important that it runs cost effectively, with minimum encryption time. In other words, it should give higher throughput. In this paper, a mechanism is proposed to improve the throughput of RC4 algorithm in multi-core processors using multithreading. The...
Provided By International Journal of Computer Applications
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Towards Building Error Resilient GPGPU Applications
GPUs (Graphics Processing Units) have gained wide adoption as accelerators for general purpose computing. They are widely used in error-sensitive applications, i.e. General Purpose GPU (GPGPU) applications However, the reliability implications of using GPUs are unclear. This paper presents a fault injection study to investigate the end-to-end reliability characteristics of...
Provided By University of Bristol
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Uplink Multicell Processing with Limited Backhaul via Successive Interference Cancellation
This paper studies an uplink multicell joint processing model in which the base-stations are connected to a centralized processing server via rate-limited digital backhaul links. Unlike previous studies where the centralized processor jointly decodes all the source messages from all base-stations, this paper proposes a suboptimal achievability scheme in which...
Provided By Institute of Electrical and Electronics Engineers
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Design of 64 Bit Parallel Prefix Adder Using Transmission Gate
Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition process. The proposed 64-bit adder is designed using four different types prefix cell operators in transmission gate technique. The power and area comparison can be made with CMOS implementation of various types parallel prefix...
Provided By EuroJournals
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Hardware / Software Co-Design Using LEON3 Processor: AES as Case Study
Nowadays many powerful public domain IP cores are available for complicated component like 32 bit processor i.e. LEON3. It needs considerable expertise and pain taking experimentation to implement a hardware/software co-design project. This paper presents step-by-step description for AES algorithm implementation on LEON3 processor. This will prove to be valuable...
Provided By International Journal of Computer Applications
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Improved Analysis and Evaluation of Real-Time Semaphore Protocols for P-FP Scheduling
Several suspension-based multiprocessor real-time locking protocols for Partitioned Fixed-Priority (P-FP) scheduling have been proposed in prior work. These protocols differ in key design choices that affect implementation complexity, overheads, and worst-case blocking, and it is not obvious which is "Best" when implemented in a real OS. In particular, should blocked...
Provided By Max Planck Institute for Software Systems
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Simulation of Genetic Algorithm Processor
Genetic Algorithms (GA) is an optimization technique for searching very large spaces that models the role of the genetic material in living organisms. A small population of individual exemplars can effectively search a large space because they contain schemata, useful substructures that can be potentially combined to make fitter individuals....
Provided By International Journal of Application or Innovation in Engineering & Management (IJAIEM)
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Design of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations
As the quantity of data transmission and reception increases, there is a gradual increase in bandwidth on demand and quality of service. This further increases data traffic which leads to loss of information, reduced accuracy and reliability. To overcome this drawback, the authors proposed coprocessor can be used for communication...
Provided By IOSR Journal of Engineering
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A Novel Approach for Faulty Node Detection with the Aid of Fuzzy Theory and Majority Voting in Wireless Sensor Networks
Wireless Sensor Networks (WSN) consist of many nodes that are usually created to identify environmental incidents. Each of these nodes includes sensor, processor, communication components (antenna), small memory, and a source of energy. In wireless sensor networks' applications, faulty nodes always cause crucial problems and error in the network. For...
Provided By AIRCC
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Lucky Scheduling for Energy-Efficient Heterogeneous Multi-Core Systems
Heterogeneous multi-core processors with big/high-performance and small/low-power cores have been proposed as an alternative design to improve energy efficiency over traditional homogeneous multi-cores. The authors make the case for proportional-share scheduling of threads in heterogeneous processor cores aimed at improving combined energy efficiency and performance. Their thread scheduling algorithm, lucky,...
Provided By Universidade Federal do Rio Grande do Sul
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An O(m) Analysis Technique for Supporting Real-Time Self-Suspending Task Systems
In many real-time and embedded systems, suspension delays may occur when tasks block to access shared resources or interact with external devices. Unfortunately, prior analysis methods for dealing with suspensions are quite pessimistic. In this paper, a novel technique is presented for analyzing soft real-time sporadic self-suspending task systems, for...
Provided By University of North Alabama
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Accurate Characterization of the Variability in Power Consumption in Modern Mobile Processors
The variability in performance and power consumption is slated to grow further with continued scaling of process technologies. While this variability has been studied and modeled before, there is lack of empirical data on its extent, as well as the factors affecting it, especially for modern general purpose microprocessors. Using...
Provided By University of Calgary
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Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors
Reducing CPU frequency and voltage is a well-known approach to reduce the energy consumption of memory-bound applications. This is based on the conception that main memory performance sees little or no degradation at reduced processor clock speeds, while power consumption decreases significantly. The authors study this effect in detail on...
Provided By Technische Universitat Dortmund
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Verilog Implementation of FPGA Based DSP Design Like FFT Processors
Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the DSP design for FFT processor and digital FIR filter. Based on the design specification, careful choice of implementation method and tools can save a lot of time and...
Provided By International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
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Jamm Scheduling: A More Efficient Approach
Scheduling involves the allocation of resources and time to tasks in such a way that certain performance requirements are met. CPU scheduling is the mechanisms of selecting a process among various processes and allocate a processor in such a way so that other processes in a ready queue wait for...
Provided By Indian Journal of Computer Science and Engineering (IJCSE)
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Who Watches the Watchmen? - Protecting Operating System Reliability Mechanisms
The authors present the design and initial evaluation of a resilient operating system architecture that leverages HW architectures combining few resilient with many non-resilient CPU cores. To this end, they build their system around a Reliable Computing Base (RCB) consisting of those software components that must work for reliable operation,...
Provided By Technische Universitat Dortmund
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Implementation of Low Power and Small Area 128-Point Mixed Radix 4-2 FFT Processor for OFDM Applications
Discrete Fourier Transform (DFT) is a very important technique used in modern Digital Signal Processing (DSP) and Telecommunications, especially for the applications involving Orthogonal Frequency Division Multiplexing (OFDM) systems. The Fast Fourier Transform (FFT) is an efficient algorithm used to compute the DFT and its inverse. In OFDM, the Inverse...
Provided By EuroJournals
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Intel Xeon Processor E7 Family: Reliability, Availability, and Serviceability
Today's businesses increasingly depend on Intel Xeon-based servers to run data-intensive and mission-critical applications. Server Reliability, Availability, and Serviceability (RAS) are crucial issues for modern enterprise IT shops that deliver mission critical applications and services, as application delivery failures can be extremely costly per hour of system downtime. Furthermore, the...
Provided By Intel
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Realization of Dualcore IBM Power5 Fine Grained Multithreaded Processor
In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The processor designed and implemented is typical RISC machines following a 4-stage pipelining having instruction fetch (I-fetch), instruction decode, executing...
Provided By International Journal of Electronics and Computer Science Engineering
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Design an E-Dictionary for Visually Impaired People Using ARM Processor
The purpose of this paper is to present a design and develop a gadget which can be used as an Electronic dictionary for visually impaired person. This design is chosen to fulfill the necessities required for a visually impaired person. In this circuit, the authors are using ARM processor due...
Provided By International Journal of Electronics and Computer Science Engineering
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Fractals Image Rendering and Compression Using GPUs
Fractal image compression provides immense advantages as compared to conventional image compressions. Though the fractal image encoding time is comparatively quite high as compared to the conventional ones but the decoding time is far less and almost instantaneous. Besides, fractal images are resolution-independent, implying that these images will render the...
Provided By The Society of Digital Information and Wireless Communications (SDIWC)
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Design, Analysis and Implementation of a New Topology of Multi Phase Synchronous Buck Converter Under Current Mode Control
This paper presents a new PWM Multi phase DC-DC converter under current mode control with an auxiliary circuit which provides zero voltage switching in order to meet the power supply requirements of the processors of modern electronic equipments like laptops, mobiles, and PDAs etc which require more than 70 A...
Provided By International Journal of Electronics and Computer Science Engineering
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Windows 7* Security with Intel® Core™ vPro™ Processors
Adapt to the speed of business and enhance Windows 7* security with the Intel® Core™ vPro™ processor.
Provided By Intel Corporation
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The Ultimate HPC Cluster Development Suite
Intel® Cluster Studio XE 2013 SP1 can help you achieve top application performance for Intel® Xeon® processor and Intel® Xeon Phi ™ coprocessor-based systems. The suite provides a comprehensive set of standards-driven C, C++, and Fortran development tools and programming models to enable developers to efficiently develop, analyze, and optimize...
Sponsored By Intel Software
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The Cortex-A8 Microprocessor
Mobile communication devices manufacture is one of the fastest growing industry today. Therefore, manufacturers are continually looking for flexible, high-performance processing solutions that can meet the needs of the low-power, cost sensitive markets. Smart phones have the ability to provide one with entertainment, gaming, internet services and seamless connectivity to...
Provided By ARM
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Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors
In the evolving sub-micron technology, importance of wire delays is growing, making it particularly attractive to use decentralized designs. A common form of decentralization adopted in processors is to partition the execution core into multiple clusters. Each cluster has a small instruction window, and a set of functional units. A...
Provided By Binghamton University
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Efficient Subsequence Search on Streaming Data Based on Time Warping Distance
Many algorithms have been proposed to deal with subsequence similarity search problem in time series data stream. Dynamic Time Warping (DTW), which has been accepted as the best distance measure in time series similarity search, has been used in many research works. SPRING and its variance were proposed to solve...
Provided By Chulalongkorn University
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Implementation of TCP/IP Stack for 3L Diamond Operating System
This paper deals with implementation of TCP/IP stack for 3L Diamond operating system. After short introduction to multiprocessor operating system 3L Diamond, main implementation issues are described. Digital signal processor module based on TMS320C6455 is used as a target platform. Processor based digital systems are used in the broad spectrum...
Provided By Brno University of Technology
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Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor With Directly Interconnected PEs
Coarse-grained Dynamically Reconfigurable Processor Arrays (DRPAs) have been received an attention as a flexible and efficient o -loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a...
Provided By Keio University
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Dynamic Voltage and Frequency Scaling for Optimal Real-Time Scheduling on Multiprocessors
Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulability improvement but also energy efficiency for the systems. In this paper, Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) techniques based on the theoretically optimal Real-Time Static Voltage...
Provided By Keio University
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Towards a Software Transactional Memory for Graphics Processors
The introduction of general purpose computing on many-core graphics processor systems, and the general shift in the industry towards parallelism, has created a demand for ease of parallelization. Software Transactional Memory (STM) simplifies development of concurrent code by allowing the programmer to mark sections of code to be executed concurrently...
Provided By EUROGRAPHICS Association
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Temperature-Aware Test Scheduling for Multiprocessor Systems-On-Chip
Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high Integrated Circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. The authors...
Provided By Northwestern University
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Evaluating Voltage Islands in CMPs under Process Variations
Parameter variations are a major factor causing power-performance asymmetry in chip multiprocessors. In this paper, the authors analyze the effects of With-In-Die (WID) process variations on chip multicore processors and then apply a variable voltage island scheme to minimize power dissipation. Their idea is based on the observation that due...
Provided By Northwestern University
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User-And Process-Driven Dynamic Voltage and Frequency Scaling
The authors describe and evaluate two new, independently-applicable power reduction techniques for power management on processors that support Dynamic Voltage and Frequency Scaling (DVFS): User-Driven Frequency Scaling (UDFS) and Process-Driven Voltage Scaling (PDVS). In PDVS, a CPU-customized profile is derived offline that encodes the minimum voltage needed to achieve stability...
Provided By Northwestern University
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Asymmetric Interactions in Symmetric Multi-Core Systems: Analysis, Enhancements and Evaluation
Multi-core architectures have spurred the recent rapid growth in high-end computing systems. While the vast majority of such multi-core processors contain symmetric hardware components, their interaction with systems software, in particular the communication stack, results in a remarkable amount of asymmetry in the effective capability of the different cores. In...
Provided By Virginia Tech
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Handwritten Digit Recognition With a Committee of Deep Neural Nets on GPUs
The competitive MNIST handwritten digit recognition benchmark has a long history of broken records since 1998. The most recent substantial improvement by others dates back 7 years (error rate 0.4%). Recently the authors were able to significantly improve this result, using graphics cards to greatly speed up training of simple...
Provided By University of Lugano
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Sort Vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs
Join is an important database operation. As computer architectures evolve, the best join algorithm may change hand. This paper reexamines two popular join algorithms - hash join and sort-merge join - to determine if the latest computer architecture trends shift the tide that has favored hash join for many years....
Provided By VLDB Endowment
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MainMemory Scan Sharing for MultiCore CPUs
Computer architectures are increasingly based on multi-core CPUs and large memories. Memory bandwidth, which has not kept pace with the increasing number of cores, has become the primary processing bottleneck, replacing disk I/O as the limiting factor. To address this challenge, the authors provide novel algorithms for increasing the throughput...
Provided By VLDB Endowment
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Efficient Implementation of Sorting on MultiCore SIMD CPU Architecture
Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Although literature abounds with various flavors of sorting algorithms, different architectures call for customized implementations to achieve faster sorting times. This paper presents...
Provided By VLDB Endowment
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Data Processing on FPGAs
Computer architectures are quickly changing toward heterogeneous many-core systems. Such a trend opens up interesting opportunities but also raises immense challenges since the efficient use of heterogeneous many-core systems is not a trivial problem. In this paper, the authors explore how to program data processing operators on top of Field-Programmable...
Provided By VLDB Endowment
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AdHoc Data Processing in the Cloud
Ad-hoc data processing has proven to be a critical paradigm for Internet companies processing large volumes of unstructured data. However, the emergence of cloud-based computing, where storage and CPU are outsourced to multiple third-parties across the globe, implies large collections of highly distributed and continuously evolving data. The authors' demonstration...
Provided By VLDB Endowment
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Fast Sparse MatrixVector Multiplication on GPUs: Implications for Graph Mining
Scaling up the sparse matrix-vector multiplication kernel on modern Graphics Processing Units (GPU) has been at the heart of numerous studies in both academia and industry. In this paper the authors present a novel non-parametric, self-tunable, approach to data representation for computing this kernel, particularly targeting sparse matrices representing power-law...
Provided By VLDB Endowment
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High Throughput Transaction Executions on Graphics Processors
OLTP (On-Line Transaction Processing) is an important business system sector in various traditional and emerging online services. Due to the increasing number of users, OLTP systems require high throughput for executing tens of thousands of transactions in a short time period. Encouraged by the recent success of GPGPU (General-Purpose computation...
Provided By VLDB Endowment
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Improving the Performance of List Intersection
List intersection is a central operation, utilized excessively for query processing on text and databases. The authors present list intersection algorithms for an arbitrary number of sorted and unsorted lists tailored to the characteristics of modern hardware architectures. Two new list intersection algorithms are presented for sorted lists. The first...
Provided By VLDB Endowment
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Parallelizing Query Optimization
Many commercial RDBMSs employ cost-based query optimization exploiting Dynamic Programming (DP) to efficiently generate the optimal query execution plan. However, optimization time increases rapidly for queries joining more than 10 tables. Randomized or heuristic search algorithms reduce query optimization time for large join queries by considering fewer plans, sacrificing plan...
Provided By VLDB Endowment
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Using Multi-Thread Technology Realize Most Short-Path Parallel Algorithm
With the development of computer, the graph theory research obtains widely takes, and the most short-path question as a model question of graph theory is already applied in many fields. Because the efficiency of the existing most short-path serial algorithm is not very high, and it is already with difficulty...
Provided By Tianjin Polytechnic University
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On the Parallelisation of MCMC by Speculative Chain Execution
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Monte Carlo (MCMC) simulations are widely used for approximate counting problems, Bayesian inference and as a means for estimating very high-dimensional integrals. As such MCMC has had a wide...
Provided By University of Warsaw
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WMTools - Assessing Parallel Application Memory Utilisation at Scale
The divergence between processor and memory performance has been a well discussed aspect of computer architecture literature for some years. The recent use of multi-core processor designs has, however, brought new problems to the design of memory architectures - as more cores are added to each successive generation of processor,...
Provided By University of Warsaw
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WMTrace - A Lightweight Memory Allocation Tracker and Analysis Framework
The diverging gap between processor and memory performance has been a well discussed aspect of computer architecture literature for some years. The use of multi-core processor designs has, however, brought new problems to the design of memory architectures - increased core density without matched improvement in memory capacity is reducing...
Provided By University of Warsaw
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Adaptive Block Pinning Based: Dynamic Cache Partitioning for Multi-Core Architectures
This paper is aimed at exploring the various techniques currently used for partitioning last level (L2/L3) caches in multicore architectures, identifying their strengths and weaknesses and thereby proposing a novel partitioning scheme known as Adaptive Block Pinning which would result in a better utilization of the cache resources in CMPs....
Provided By Birla Institute of Technology and Science
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Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design
A typical processor central processing unit devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in...
Provided By Om College Of Engineering
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Design of IEEE 1588 Based Precision Time Protocol Using PSOS
The widespread clock synchronization standard, IEEE 1588, is purely master-slave based. The inherent disadvantage is that a failure of the master requires the election of a new one, during which the network nodes cannot be synchronized. This paper proposes a compatible extension to the standard introducing architecture for fault-tolerant and...
Provided By International Journal of Soft Computing and Engineering (IJSCE)
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Genetic Algorithm for Multiprocessor Task Scheduling
MultiProcessor Task Scheduling (MPTS) is an important and computationally difficult problem. Multiprocessors have emerged as a powerful computing means for running real-time applications especially due to limitation of uni-processor system for not having sufficient enough capability to execute all the tasks. This paper describes multiprocessor task scheduling in the form...
Provided By International Journal of Computer Science and Management Studies
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An Efficient BSP/CGM Algorithm for the Matrix Chain Ordering Problem
The Matrix Chain Ordering Problem (MCOP) is widely used in computer and specially in combinatorial optimization. Even though there has been intensive work for the parallelization of dynamic programming on PRAM, systolic arrays among others, its parallel version on BSP/CGM is still to be done. In the former work, the...
Provided By Universite de Picardie Jules Verne
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Security in Cloud Computing
Learn about how leading cloud solution providers are taking advantage of the advanced security technologies built into the latest generation of Intel® Xeon® processor-based servers to meet these challenges.
Provided By Intel Corporation
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Windows 7* Security with Intel® Core™ vPro™ Processors
Adapt to the speed of business and enhance Windows 7* security with the Intel® Core™ vPro™ processor.
Provided By Intel Corporation
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Research on Model Checking Cellular Automata
Cellular Automata (CA) is a model for describing state evolution system with local communication. It can be used to model artificial life and traffic flow, etc. The expression ability of the Cellular Automata is powerful. But the property analysis of it is in general a hard problem. In this paper,...
Provided By Shanghai University
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Domain Decomposition Method on GPU Cluster
Pallalel GPGPU computing for lattice QCD simulations has a bottleneck on the GPU to GPU data communication due to the lack of the direct data exchanging facility. In this work the authors investigate the performance of quark solver using the Restricted Additive Schwarz (RAS) preconditioner on a low cost GPU...
Provided By Hiroshima University
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ENEA MULTICORE: High Performance Packet Processing Enabled With a Hybrid SMP/AMP OS Technology
This paper starts by describing the widely accepted multiprocessing software design models, and some of their benefits and drawbacks. After that, a few simple packet processing use cases are described, aiming to illuminate the pain points of a strict AMP multiprocessing approach. Finally, one introduce Eneas OSE Multi core Edition...
Provided By ENEA
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Cluster Computing Helps Researchers Thrive: AMD and HP Help Purdue University Build a New HPC Center
AMD and HP wanted to support Purdue University researchers with a cost-effective supercomputing solution for demanding simulations and data processing across a range of academic disciplines and provide supplemental High Performance Computing (HPC) support for researchers with the National Science Foundation's TeraGrid. As a solution Purdue's Coates cluster - currently...
Provided By Advanced Micro Devices
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Triple Eight Race Engineering Was Able to Design and Build a Winning Race Car in Record Time, With Workstations Running AMD Opteron Processors and ATI Professional Graphics
Triple Eight Race Engineering began developing its car for the 2007 race season but hit a major snag when the British Touring Car Championship (BTCC) adopted a new set of regulations. As a result, the car it had been racing could no longer compete and they were forced to switch...
Provided By Advanced Micro Devices
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Online Retail Mortgage Lender Quicken Loans Supports Massive Growth and Delivers Optimal Customer Service With the Help of VMware and Microsoft Software, HP and Sun Servers, and AMD Opteron Processors
Quicken Loans, Inc. wanted to support massive ongoing company growth while continuing to maintain a high level of customer service and reduce server sprawl in the datacenter, as well as heat emissions. The challenge was to ensure optimal performance for today and tomorrow. A virtualization environment was established on AMD...
Provided By Advanced Micro Devices
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Designing and Optimizing the Fetch Unit for a RISC Core
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing. On the other hand, having a design procedure (used to solve the problems related to the design of a single processing core)...
Provided By Amirkabir University of Technology