Teridian SoC Exploitation: Exploration of Harvard Architecture Smart Grid Systems

The Teridian system-on-a-chip platform wraps a complete system around a modified 8051 core, with additional features for chip security to block debug functionality and external access to memory. Additionally, the Harvard architecture design sets relatively rigid barriers between code and data (as opposed to x86/64), which presents an unintentional security barrier, somewhat similar to robust hardware DEP on x86/64 platforms.

Provided by: SecurityTube.net Topic: Hardware Date Added: Dec 2014 Format: Webcast

Find By Topic