2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation

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Executive Summary

The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly. A fully reconfigurable architecture for address generation in WiMAX channel interleaver is presented, which consume k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX.

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