A 12-Bit 3.125 MHz Bandwidth 0-3 MASH Delta-Sigma Modulator

Date Added: Jul 2009
Format: PDF

This paper demonstrates a 12-bit 0 - 3MASHdelta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 clock frequency of 50 MHz and achieves a peak SNDR of 73.9 dB (77.2 dB Peak SNR) and consumes 24mWfrom a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0 - 3MASHarchitecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).