A 12b 100MS/s Highly Power Efficient Pipelined ADC for Communication Applications
12 bits 100 MS/s pipelined ADC with a high ENOB is proposed for communication applications especially for Wireless Networks. The proposed ADC achieves low power, high resolution and high speed operation due to deliberately design of a low power high performance operational amplifier for the pipeline stages. In addition, more power reduction is achieved by proper power and parameters scaling for the stages granting the proposed ADC remarkably distinguished power efficiency compared to other ones. The ADC has been designed and simulated by HSPICE in 0.18 ?m CMOS technology.