A 5.42nW/kB Retention Power Logic-Compatible Embedded DRAM With 2T Dual-Vt Gain Cell for Low Power Sensing Applications

A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8? longer retention time, 5? lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported. With an area-efficient single inverter sensing scheme designed for R/W speed compatibility with ultralow power processors, 58% array efficiency is maintained for memories as small as 2kb and for as few as 32 bits per bitline.

Provided by: University of Michigan Topic: Storage Date Added: Jan 2011 Format: PDF

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