A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications
A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%.