A Better X86 Memory Model: X86-TSO

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Executive Summary

Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory models, typically described in ambiguous prose, which lead to widespread confusion. These are prime targets for mechanized formalization. In previous work the produced a rigorous x86-CC model, formalizing the Intel and AMD architecture specifications of the time, but those turned out to be unsound with respect to actual hardware, as well as arguably too weak to program above. They discuss these issues and present a new x86-TSO model that suffers from neither problem, formalized in HOL4. They believe it is sound with respect to real processors, reflects better the vendors intentions, and is also better suited for programming.

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