Date Added: Nov 2011
Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnection, and hence reducing them is an important problem. Application-specific designs have non-uniform network utilization, thereby requiring a buffer-sizing approach that tackles the non-uniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, the authors propose a two-phase algorithm to size the switch buffers in Network-on-Chips (NoCs) considering support for multiple-frequency islands. Their algorithm considers both the static and dynamic effects when sizing buffers.