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Given the multi-core microprocessor revolution, the authors argue that the architecture research community needs a dramatic increase in simulation capacity. They believe FPGA Architecture Model Execution (FAME) simulators can increase the number of useful architecture research experiments per day by two orders of magnitude over Software Architecture Model Execution (SAME) simulators. To clear up misconceptions about FPGA-based simulation methodologies, they propose a FAME taxonomy to distinguish the cost-performance of variations on these ideas. They demonstrate their simulation speedup claim with a case study wherein they employ a prototype FAME simulator, RAMP Gold, to research the interaction between hardware partitioning mechanisms and operating system scheduling policy.
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