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A Scalable hierarchical architecture based Code-Division Multiple Access (CDMA) is proposed for high performance Network-on-Chip (NoC). This hierarchical architecture provides the integration of a large number of IPs in a single on-chip system. The network encoding and decoding schemes for CDMA transmission are provided. The proposed CDMA NoC architecture is compared to the conventional architecture in terms of latency, area and power dissipation. The overall area required to implement the proposed CDMA NoC design is reduced by 24.2%. The design decreases the latency of the network by 40%. The total power consumption required to achieve the proposed design is also decreased by 25%.
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