A Chip Architecture for Compressive Sensing Based Detection of Ic Trojans
The authors present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a Circuit Under Test (CUT). They describe their designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Their architecture achieves approximately a 10? speedup and 1000? reduction in output bandwidth while incurring a small area overhead.