A Code Layout Framework for Embedded Processors With Configurable Memory Hierarchy

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Executive Summary

Several embedded processors now support configurable memory hierarchies to exploit application specific workload characteristics. To take advantage of memory reconfigurability, automated software optimization techniques are generally lacking and application developers often resort to a hand tuned code layout. This not only increases the time to market of embedded products but may also result in an inefficient mapping. To address this issue, the authors have developed a framework which incorporates profile guided code layout algorithms to efficiently map code on the available L1 code memory configurations. Given a L1 memory configuration, they show that the code layout problem can be mapped to a NP-complete Knapsack problem or to a combination of Knapsack problem and a graph coarsening problem.

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