A Combinatorial Application of Necklaces: Modeling Individual Link Failures in Parallel Network-on-Chip Interconnect Links
The advent of the multicore era has made the execution of more complex software applications more efficient and faster. On-chip communication among the processing cores, in the form of packetized messages, is managed with the use of on-chip networks (NoCs). Routers handling on-chip communication are point-to-point topologically interconnected using parallel links laid onto the silicon surface comprising a number of individual parallel wires. With the underlying interconnect structure becoming denser, due to improvements in CMOS technology, parallel links become susceptible to wear-out, with permanent link failures inhibiting communication completely and indefinitely.