Date Added: Sep 2010
Tuning cache hierarchies in platforms for embedded systems can significantly reduce energy consumption. In this paper, the authors combined two optimization methods for tuning both instruction and data cache configurations in a two-level memory hierarchy, where both levels have separate instruction and data caches. This kind of hierarchy allows them to evaluate instruction and data caches branches separately, although previous approaches have applied the same method for both branches of the hierarchy. This paper evaluates several methods intended for two-level hierarchies, and the results showed that when they combine different methods for each branch of the hierarchy, results can be improved.