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The authors have investigated the Network-on-Chip (NOC) as an emerging on-chip interconnects technology, to understand and compare its impact on global communication delays, and power consumption in a System-on-Chip (SOC). In order to achieve this, a hypothetical SOC comprising of multiple 32 bit processors and memory cores is designed using a NOC architecture and synthesized using Cadence tools and 180 nm process technologies. The same SOC is redesigned using the Advanced Microcontroller Bus Architecture (AMBA), and the performance of the two interconnect architectures is compared.
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