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A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths

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Executive Summary

Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic can be complex and expensive. This paper presents a complete synthesis flow that generates self-timed combinational networks from conventional Boolean networks. The boolean network is partitioned into small function blocks which are then synthesized using self-timed techniques. The procedure employs relaxation optimizations to distribute the overheads associated with self-timed networks between function-blocks. Relaxation is incorporated into the function block synthesis procedures, meaning the optimizations can be applied at a much finer granularity than previously possible.

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