Download now Free registration required
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. The authors make three contributions: The authors describe a simple power-down policy for exploiting low power modes of modern DRAMs; they show how the idea of adaptive history-based memory schedulers can be naturally extended to manage power and energy; and for situations in which additional DRAM power reduction is needed, the authors present a throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands.
- Format: PDF
- Size: 280.9 KB