Date Added: Nov 2010
Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, the authors present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Their multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, they extend the multiplier with an accurate scalar product unit for IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error.