A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs
A domain extension algorithm to correct the comparator offsets of pipeline Analog-to-Digital Converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the Spurious-Free Dynamic Range (SFDR), the Total Harmonic Distortion (THD), the Signal-to-Noise Ratio (SNR) and the minor analog and digital circuit modifications.