Date Added: Jun 2009
Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because non-volatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, the authors study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) as the main memory for a 3D stacked chip. The main challenges they face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology.