A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several arithmetic cores for parallel processing while supporting high numerical precision with finite logical resources. This paper introduces an arithmetic architecture that uses run-time partial reconfiguration to dynamically adapt its numerical precision, without requiring significant additional logical resources.