A Flexible Bufferless H-ARQ Processor Based on Dataflow Scheduling
Flexible radio is a challenging way to implement communication standards. In theses standards, Hybrid ARQ (H-ARQ) is admitted as a usual error control protocol. H-ARQ is a cross-layer protocol, offering a number of different possible versions, with multiple instantiations running concurrently. In this context, designing a flexible H-ARQ component is a necessity. This paper presents an H-ARQ processor able to cope with the possible versions of the protocol and any number of instantiations. Based on a modified hardware/software partitioning, it is able to dynamically reconfigure its operation mode.